A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled to the gate input. A constant positive current is input to one of the source/drain regions. The remaining source/drain region is either allowed to float, is coupled to a ground potential, or is coupled to the first source/drain region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for operating a CMOS memory system comprising a processor coupled to an NROM array that comprises a plurality of NROM cells, each NROM cell having a gate and two source/drain regions, the method comprising: applying a constant voltage to the gate of each NROM cell to be erased; applying a constant positive current into a first of the source/drain regions of each NROM cell to be erased; applying a ground potential to the remaining source/drain region of each NROM cell to be erased, wherein a nitride charge storage layer that is being erased is a continuous blanket over the NROM array such that the nitride charge storage layer does not cover the gate and an oxide layer between the gate and the nitride charge storage layer; monitoring the first source/drain region for a predetermined voltage level; and ending the method for operating when the predetermined voltage level is reached.
2. The method of claim 1 wherein applying the constant voltage, applying the constant positive current, and applying the ground potential are performed in response to commands received over data, control, and address buses from the processor.
3. The method of claim 1 wherein the constant gate voltage is in a range of 0 to −12V, the constant positive current is in a range of 0.1 nA to 10 μA per cell, and the method for operating has a duration in a range of 1 μs to 1 second.
4. The method of claim 1 wherein the CMOS memory system is formed on a single integrated circuit die.
5. The method of claim 1 wherein the processor is coupled to the NROM array over data, control, and address buses.
6. The method of claim 1 wherein each NROM cell stores one data bit.
7. A method for operating a CMOS memory system comprising a processor coupled to an NROM array that comprises a plurality of NROM cells, each NROM cell having a gate, two source/drain regions, and a nitride layer, the method comprising: biasing the gate of each NROM cell to be erased with a first predetermined voltage; injecting a positive current into a first source/drain region of each NROM cell to be erased; grounding the remaining source/drain region of each NROM cell to be erased, wherein the nitride layer that is being erased is a continuous blanket over the NROM array such that the nitride layer does not cover the gate and an oxide layer between the gate and the nitride layer; monitoring the first source/drain region for a predetermined voltage level; and ending the method for operating when the predetermined voltage level is reached.
8. The method of claim 7 wherein the first predetermined voltage is a negative voltage.
9. The method of claim 7 wherein the positive current is in a range of gate induced drain leakage.
10. The method of claim 7 and further including ending biasing and injecting when the first source/drain region reaches a second predetermined voltage.
11. A method for operating a CMOS memory system comprising a processor coupled to an NROM array that comprises a plurality of NROM cells, each NROM cell having a gate, two source/drain regions, and a nitride layer, the method comprising: biasing each gate of the NROM cells to be erased with a negative voltage; injecting a positive current that is greater than 0.10 nA into a first source/drain region of each NROM cell to be erased; biasing with zero volts the remaining source/drain region of each NROM cell to be erased, wherein the nitride layer that is being erased is a continuous blanket over the NROM array such that the nitride layer does not cover the gate and an oxide layer between the gate and the nitride layer; monitoring the first source/drain region for a predetermined voltage; and ending the method for operating when the predetermined voltage is achieved.
12. The method of claim 11 wherein the gate induced drain leakage remains substantially constant throughout the method for operating.
13. The method of claim 11 wherein the NROM array is embedded in the CMOS memory system.
14. The method of claim 11 wherein the negative voltage is −7V.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 15, 2006
December 29, 2009
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