A semiconductor device that suppresses partial discharging to a semiconductor substrate caused by local concentration of current. The semiconductor device includes a semiconductor substrate, a gate electrode buried in the semiconductor substrate, a conductor buried in the semiconductor substrate further inward from the gate electrode, a wiring layer formed in the semiconductor substrate in connection with the conductor, and an insulation film arranged between the gate electrode and the conductor. The conductor is higher than the surface of the semiconductor substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a semiconductor substrate having a surface; a wiring layer buried in the semiconductor substrate; a conductor buried in the semiconductor substrate and made of a metallic material or polysilicon, with the conductor having a first end connected to the wiring layer and a second end exposed from the semiconductor substrate; and an insulation film arranged between the semiconductor substrate and the conductor, wherein the first end of the conductor extends into the wiring layer from an end of the insulation film and the second end of the conductor extends outward from the surface of the semiconductor substrate, wherein the wiring layer includes a groove that comes in contact with the first end of the conductor.
2. The semiconductor device according to claim 1 , wherein the insulation film is in contact with the semiconductor substrate.
3. The semiconductor device according to claim 1 , further comprising: a conductive layer formed on the semiconductor substrate, wherein current flows between the conductor, the wiring layer, the semiconductor substrate, and the conductive layer.
4. The semiconductor device according to claim 1 , wherein: the insulation film, which has a surface, further covers the surface of the semiconductor substrate; and said part of the conductor is higher than the surface of the insulation film.
5. The semiconductor device according to claim 1 , wherein the conductor has at least one first plane and at least one second plane that are alternately arranged adjacent to each other, with the adjacent first and second planes being angled from each other at an obtuse angle.
6. The semiconductor device according to claim 1 , wherein the part of the conductor includes a curved surface.
7. A semiconductor device comprising: a semiconductor substrate; a wiring layer buried in the semiconductor substrate; a conductor buried in the semiconductor substrate, with the conductor having a first end connected to the wiring layer and a second end exposed from the semiconductor substrate; and an insulation film arranged between the semiconductor substrate and the conductor, wherein the conductor has at least one first plane and at least one second plane that are arranged adjacent to each other, with the second plane having a part that is not in contact with the insulation film, wherein the adjacent first and second planes of the conductor form therebetween an inflection point at which the adjacent first and second planes are angled from each other at an obtuse angle.
8. The semiconductor device according to claim 7 , wherein the insulation film is in contact with the semiconductor substrate.
9. The semiconductor device according to claim 7 , further comprising: a conductive layer formed on the semiconductor substrate, wherein current flows between the conductor, the wiring layer, the semiconductor substrate, and the conductive layer.
10. The semiconductor device according to claim 7 , wherein the conductor includes a curved upper surface.
11. The semiconductor device according to claim 7 , wherein the wiring layer includes a groove that comes in contact with part of the conductor.
12. A semiconductor device comprising: a semiconductor substrate having a surface; a wiring layer buried in the semiconductor substrate; a conductor buried in the semiconductor substrate, with the conductor having a first end connected to the wiring layer and a second end exposed from the semiconductor substrate; a gate electrode buried in the semiconductor substrate, wherein a part of the semiconductor substrate is arranged between the conductor and the gate electrode; and an insulation film arranged between the semiconductor substrate and the conductor, wherein the second end of the conductor extends outward from the surface of the semiconductor substrate, wherein the wiring layer includes a groove that comes in contact with the first end of the conductor.
13. The semiconductor device according to claim 12 , further comprising: a conductive layer formed on the semiconductor substrate, wherein current flows between the conductor, the wiring layer, the semiconductor substrate, and the conductive layer.
14. The semiconductor device according to claim 12 , wherein: the insulation film, which has a surface, further covers the surface of the semiconductor substrate; and said part of the conductor is higher than the surface of the insulation film.
15. The semiconductor device according to claim 12 , wherein the conductor has at least one first plane and at least one second plane that are alternately arranged adjacent to each other, with the adjacent first and second planes being angled from each other at an obtuse angle.
16. The semiconductor device according to claim 12 , wherein the part of the conductor includes a curved surface.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 28, 2007
January 12, 2010
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