A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing an integrated circuit having trench isolation regions in a substrate including germanium, the method comprising: forming a silicon nitride layer above the substrate; selectively etching the silicon nitride layer to form apertures associated with locations of the trench isolation regions; forming trenches in the substrate at the locations; and forming oxide liners in the trenches of the substrate in a low temperature process; wherein the low temperature process utilizes SiH 4 gas and is performed at a temperature below 700° C.
2. The method of claim 1 , wherein the low temperature process is an HDP oxide deposition process without NH 3 .
3. The method of claim 2 , wherein the low temperature process is performed at a temperature below 650° C.
4. The method of claim 1 , wherein the low temperature process is a dual frequency RF power PECYD process.
5. The method of claim 4 , wherein the low temperature process is performed at a temperature below 550° C.
6. The method of claim 4 , further comprising: performing a rapid thermal anneal for approximately 30 seconds at a temperature below 1000° C.
7. A method of manufacturing an integrated circuit having trench isolation regions in a substrate including germanium, the method comprising: forming a silicon nitride layer above the substrate; selectively etching the silicon nitride layer to form apertures associated with locations of the trench isolation regions; forming trenches in the substrate at the locations; and forming oxide liners in the trenches of the substrate in a low temperature process; wherein the low temperature process is a UVO process performed at a temperature of less than 600° C.
8. The method of claim 7 , wherein the low temperature process is below 550° C.
9. The method of claim 7 , wherein the UVO process uses a first UV light with a wavelength of approximately 185 nm.
10. The method of claim 9 , further comprising: emitting a second UV light having a wavelength of approximately 254 nm for further decomposition, after forming the oxide liners.
11. A method of manufacturing an integrated circuit having trench isolation regions in a substrate including germanium, the method comprising: forming a silicon nitride layer above the substrate; selectively etching the silicon nitride layer to form apertures associated with locations of the trench isolation regions; forming trenches in the substrate at the locations; and forming oxide liners in the trenches of the substrate in a low temperature process; wherein the low temperature process is an ALD process using SiH 4 gas.
12. The method of claim 11 , wherein the ALD process uses a pulse cycle process.
13. The method of claim 12 , wherein the pulse cycle process alternately turns on and off SiH 4 and O 2 gas flows.
14. The method of claim 11 , wherein the gas flows are turned on in time intervals between approximately 10-30 seconds.
15. A method of forming shallow trench isolation regions in a semiconductor layer comprising germanium, the method comprising: providing a hard mask layer above the semiconductor layer; providing a photoresist layer above the hard mask layer; selectively removing portions of the photoresist layer at locations in a photolithographic process; removing the hard mask layer at the locations; forming trenches in the semiconductor layer under the locations; and forming a liner in the trenches using ultraviolet light in a low temperature process at a temperature below approximately 600° C.
16. The method of claim 15 , further comprising providing a pad oxide layer above a strained silicon layer before the providing a hard mask layer step.
17. The method of claim 16 , further comprising removing the pad oxide layer at the locations before the step of forming trenches in the hard mask layer under the locations.
18. The method of claim 15 , further comprising: providing an insulative material in the trenches to form the shallow trench isolation regions; and removing the hard mask layer in a wet bath.
19. The method of claim 18 , wherein the wet bath includes acid.
20. The method of claim 15 , wherein the low temperature process is below 550° C.
21. A method of forming shallow trench isolation regions in a semiconductor layer, the method comprising: providing a hard mask layer above the semiconductor layer; providing a photoresist layer above the hard mask layer; selectively removing portions of the photoresist layer at locations in a photolithographic process; removing the hard mask layer at the locations; forming trenches in the semiconductor layer under the locations; and forming a liner in the trenches using ultraviolet light; wherein the forming a liner step is a low temperature process below 700° C.; and wherein the liner is silicon dioxide grown in an oxygen atmosphere.
22. The method of claim 21 , wherein the liner is 200-500 Å thick.
23. The method of claim 21 , further comprising providing a pad oxide layer before the providing a hard mask layer step.
24. The method of claim 21 , further comprising removing the pad oxide layer at the locations before forming the trenches.
25. The method of claim 21 , further comprising providing an insulative material in the trenches to form the trench isolation regions.
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January 14, 2003
January 19, 2010
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