Semiconductor memory device capable of achieving narrower distribution width of threshold voltages of memory cells and method of data write in the same

1. A semiconductor memory device, comprising: a memory array having a plurality of memory cells and divided into first and second memory mats; a selection circuit designating prescribed areas having an identical address, of respective said first and second memory mats of said memory array, that are data write targets, based on external address input; first and second data latch portions holding first and second write data groups defining application of program pulses to memory cells in the prescribed areas of said first and second memory mats designated by said selection circuit, respectively; first and second write drivers provided corresponding to said first and second data latch portions respectively, for applying the program pulses to the memory cells included in selected said prescribed areas in accordance with said first and second write data groups; a write/verify control portion for controlling at least one of said first and second write drivers to perform data write and verify write in which the program pulse is applied to the memory cell included in said selected prescribed area; and a sense amplifier portion for performing data read after said data write and said verify write into the memory cell included in said selected prescribed area that is said data write target; said write/verify control portion giving an instruction to perform data write into the prescribed area of one of said first and second memory mats based on said write data group held in one of said first and second data latch portions, and repeatedly giving an instruction to perform said verify write into the memory cell included in said selected prescribed area until verify is completed, based on a result of verify obtained based on comparison between a data group read by said sense amplifier portion from the memory cell included in said selected prescribed area and said write data group, and in a write sequence, said write/verify control portion giving an instruction to perform data write into the memory cell included in the prescribed area of said second memory mat after verify of the memory cell included in the prescribed area of said first memory mat is completed.

2. A semiconductor memory device, comprising: a memory array having a plurality of memory cells and divided into first and second memory mats; a selection circuit designating prescribed areas having an identical address, of respective said first and second memory mats of said memory array, that are data write targets, based on external address input; first and second data latch portions holding first and second write data groups defining application of program pulses to memory cells in the prescribed areas of said first and second memory mats designated by said selection circuit, respectively; first and second write drivers provided corresponding to said first and second data latch portions respectively, for applying the program pulses to the memory cells included in selected said prescribed areas in accordance with said first and second write data groups; and a write control portion for controlling at least one of said first and second write drivers to perform data write in which the program pulse is applied to the memory cell included in said selected prescribed area; in a write sequence, said write control portion giving an instruction to perform data write in which the program pulses are applied at different timing to one and another of the memory cells included in said selected prescribed areas of said first and second memory mats.

3. The semiconductor memory device according to claim 2 , wherein said write control portion controls at least one of said first and second write drivers to further perform verify write in which the program pulse is applied again at different timing to the memory cell included in said selected prescribed area, said semiconductor memory device further comprises a sense amplifier portion for performing data read after said data write and said verify write into the memory cell included in said selected prescribed area that is said data write target, and said write control portion gives an instruction to perform said verify write into the memory cell included in said selected prescribed area based on a result of verify obtained based on comparison between a data group read by said sense amplifier portion from the memory cell included in said selected prescribed area and at least one of said first and second write data groups.

4. The semiconductor memory device according to claim 3 , wherein said sense amplifier portion includes first and second sense amplifier circuits provided corresponding to said first and second memory mats respectively, for performing parallel data read after said data write and said verify write into the memory cell included in said selected prescribed area that is said data write target, and said semiconductor memory device further comprises first and second verify circuits provided corresponding to said first and second memory mats respectively, for outputting in parallel results of verify based on comparison between the data groups read by respective said first and second sense amplifier circuits from the memory cells included in said selected prescribed areas and said first and second write data groups, respectively.

5. The semiconductor memory device according to claim 3 , wherein said sense amplifier portion includes first and second sense amplifier circuits provided corresponding to said first and second memory mats respectively, for performing data read after said data write and said verify write into the memory cell included in said selected prescribed area that is said data write target, said semiconductor memory device further comprises first and second verify circuits provided corresponding to said first and second memory mats respectively, for outputting results of verify based on comparison between the data groups read by respective said first and second sense amplifier circuits from the memory cells included in said selected prescribed areas and said first and second write data groups, respectively, and said write control portion gives an instruction to perform, prescribed number of times, said verify write into the memory cells included in said selected prescribed areas of said first and second memory mats based on the results of verify output in parallel from said first and second verify circuits, thereafter repeatedly gives an instruction to perform said verify write into the memory cell included in the prescribed area of said first memory mat until verify is completed based on the result of verify obtained based on comparison between the data group read by said first sense amplifier circuit from the memory cell included in said selected prescribed area and said first write data group, and gives an instruction to perform said verify write into the memory cell included in the prescribed area of said second memory mat after verify of the memory cell included in the prescribed area of said first memory mat is completed.

6. A method of writing data in a semiconductor memory device including a memory array having a plurality of memory cells and divided into first and second memory mats, a selection circuit designating prescribed areas having an identical address, of respective said first and second memory mats of said memory array, that are data write targets, based on external address input, first and second data latch portions holding first and second write data groups defining application of program pulses to memory cells in the prescribed areas of said first and second memory mats designated by said selection circuit respectively, first and second write drivers provided corresponding to said first and second data latch portions respectively, for applying the program pulses to the memory cells included in selected said prescribed areas in accordance with said first and second write data groups, a write/verify control portion for controlling at least one of said first and second write drivers to perform data write and verify write in which the program pulse is applied to the memory cell included in said selected prescribed area, first and second sense amplifier circuits for performing data read after said data write and said verify write into the memory cell included in said selected prescribed area that is said data write target, and first and second verify circuits provided corresponding to respective said first and second sense amplifier circuits, for performing verify determination in which results of verify are output based on comparison between data groups read by respective said first and second sense amplifier circuits and first and second write data groups, comprising the steps of: inputting said first and second write data groups to said first and second data latch portions, respectively; instructing said first write driver to perform said data write into the memory cell of the first memory mat included in said selected prescribed area in accordance with said first write data group held in said first data latch portion; performing said verify determination in which said result of verify is output from said first verify circuit based on comparison between the data group read by said first sense amplifier circuit from the memory cell of the first memory mat included in said selected prescribed area and said first write data group; repeatedly instructing said first write driver to perform said verify write into the memory cell of the first memory mat included in said selected prescribed area and performing said verify determination until verify is completed, based on said result of verify from said first verify circuit; and instructing said second write driver to perform data write into the memory cell included in the prescribed area of said second memory mat after verify of the memory cell of said first memory mat included in the prescribed area is completed.

7. A method of writing data in a semiconductor memory device including a memory array having a plurality of memory cells and divided into first and second memory mats, a selection circuit designating prescribed areas having an identical address, of respective said first and second memory mats of said memory array, that are data write targets, based on external address input, first and second data latch portions holding first and second write data groups defining application of program pulses to memory cells in the prescribed areas of said first and second memory mats designated by said selection circuit respectively, first and second write drivers provided corresponding to said first and second data latch portions respectively, for applying the program pulses to the memory cells included in selected said prescribed areas in accordance with said first and second write data groups, and a write control portion for controlling at least one of said first and second write drivers to perform data write in which the program pulse is applied to the memory cell included in said selected prescribed area, comprising the steps of: inputting said first and second write data groups to said first and second data latch portions, respectively; and instructing said first and second write drivers to perform data write in which the program pulses are applied to the memory cells included in said selected prescribed areas of said first and second memory mats in accordance with said first and second write data groups input to said first and second data latch portions; and said first and second write drivers being instructed to perform, at different timing, data write into the memory cells included in said selected prescribed areas of said first and second memory mats.

8. A method of writing data in a semiconductor memory device including a memory array having a plurality of memory cells and divided into first and second memory mats, a selection circuit designating prescribed areas having an identical address, of respective said first and second memory mats of said memory array, that are data write targets, based on external address input, first and second data latch portions holding first and second write data groups defining application of program pulses to memory cells in the prescribed areas of said first and second memory mats designated by said selection circuit respectively, first and second write drivers provided corresponding to said first and second data latch portions respectively, for applying the program pulses to the memory cells included in selected said prescribed areas in accordance with said first and second write data groups, a write/verify control portion for controlling at least one of said first and second write drivers to perform data write and verify write in which the program pulse is applied to the memory cell included in said selected prescribed area, first and second sense amplifier circuits for performing data read after said data write and said verify write into the memory cell included in said selected prescribed area that is said data write target, and first and second verify circuits provided corresponding to respective said first and second sense amplifier circuits, for performing verify determination in which results of verify are output based on comparison between read data groups from respective said first and second sense amplifier circuits and corresponding write data groups, comprising the steps of: inputting said first and second write data groups to said first and second data latch portions, respectively; instructing said first and second write drivers to perform, at different timing, said data write into the memory cells of said first and second memory mats included in said selected prescribed areas in accordance with said first and second write data groups held in said first and second data latch portions, respectively; performing said verify determination in which said results of verify are output in parallel from said first and second verify circuits based on comparison between the data groups read by said first and second sense amplifier circuits from the memory cells of the first and second memory mats included in said selected prescribed areas and said first and second write data groups; instructing said first and second write drivers to perform, at different timing, said verify write into the memory cells of the first and second memory mats included in said selected prescribed areas respectively, based on said results of verify from said first and second verify circuits; repeating prescribed number of times the steps of performing said verify determination in which said results of verify are output in parallel from said first and second verify circuits and giving an instruction to perform, at different timing, said verify write into the memory cells of the first and second memory mats included in said selected prescribed areas; performing said verify determination in which said result of verify is output from said first verify circuit, based on comparison between the data group read by said first sense amplifier circuit from the memory cell of the first memory mat included in said selected prescribed area and said first write data group, after sequentially repeating said steps said prescribed number of times; instructing said first write driver to perform said verify write into the memory cell of the first memory mat included in said selected prescribed area, based on said result of verify from said first verify circuit; sequentially repeating the steps of performing said verify determination in which said result of verify is output from said first verify circuit and giving an instruction to perform said verify write into the memory cell of the first memory mat included in said selected prescribed area until verify is completed; and giving an instruction to perform said verify write into the memory cell included in the prescribed area of said second memory mat after verify of the memory cell included in the prescribed area of said first memory mat is completed.