Noise measuring circuitry of the present invention can be used to observe power supply noise waveforms, ground level noise waveforms, and a spatial distribution of noise at different positions in an integrated circuit having plural circuit blocks that perform digital signal processing, by being integrated into the integrated circuit (i.e., embedded), distributed at different positions. The distributed noise measuring circuitry can be manufactured using a CMOS process to manufacture the integrated circuit. The power supply noise measuring circuit and the ground level noise measuring circuit comprise a source follower, a select read out switch, and source-grounded amplifier. These noise measuring circuits can be configured by several (about 6) MOS transistors, so the layout for the measuring circuit can be small and can be achieved by using a logic gate circuit of the same size as that of a standard cell type logic gate circuit. As for the output of the noise measuring circuits, the output current of said source-grounded amplifier is connected to the current bus line, the outputted current is amplified and the amplified current is read by driving the external resistance load circuit. Plural noise measuring circuits can be connected parallel to the current bus line. Measuring multiple noise points in the main integrated circuit can be achieved by reading out the output current.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor integrated circuit comprising plural circuit blocks, which perform digital signal processing, wherein noise measuring circuits are embedded into distributed arrangement positions in said semiconductor integrated circuit, wherein a power supply noise waveform, a ground level noise waveform, and a spatial distribution of noise occurring positions are outputted by said noise measuring circuits, and wherein each of said noise measuring circuits comprises: a source follower connecting a power supply line of said integrated circuit to an input node of said noise measuring circuit; a signal conversion amplifier circuit converting voltage-input to current-output which input is an output of said source follower; and a current readout circuit for reading out an output current of said signal conversion amplifier circuit.
2. The semiconductor integrated circuit according to claim 1 , wherein each of said noise measuring circuits includes a select circuit which to activate each noise measuring circuit selectively.
3. The semiconductor integrated circuit according to claim 1 , wherein each of said noise measuring circuits further comprises a sampling switch circuit to an output node of said source follower.
4. The semiconductor integrated circuit according to claim 1 , wherein said current readout circuit of each noise measuring circuit is commonly shared.
5. A diagnosis analysis method for a semiconductor integrated circuit, comprising: performing a malfunction diagnosis, an error analysis, a malfunction prediction, and an error prediction of said semiconductor integrated circuit based on an actual noise data obtained from said integrated circuit wherein said noise measuring circuits according to claim 1 are embedded in said integrated circuit.
6. A manufacturing process of a semiconductor integrated circuit including a sequential process for a designing process, a manufacturing process, and a testing (evaluating) process for said semiconductor integrated circuit wherein: said manufacturing process comprises a step for embedding noise measuring circuits according to claim 1 into distributed arrangement positions in said semiconductor integrated circuit; and said testing process comprises a step for measuring and evaluating said power supply noise waveform, ground level noise waveform, and a spatial distribution data by said noise measuring circuit.
7. The manufacturing process according to claim 6 , wherein said noise measuring circuits are automatically embedded into said positions of said integrated circuit by applying a standard cell base automatic wire layout designing method.
8. The manufacturing process according to claim 6 , wherein a built-in self test is performed by correlating a select logic of said noise measuring circuit to a test mode (a test pattern) logic of said integrated circuit.
9. A semiconductor integrated circuit comprising plural circuit blocks, which perform digital signal processing, wherein noise measuring circuits are embedded into distributed arrangement positions in said semiconductor integrated circuit, wherein a power supply noise waveform, a ground level noise waveform, and a spatial distribution of noise occurring positions are outputted by said noise measuring circuits, and wherein each of said noise measuring circuits comprises: a p-type source follower connecting a ground line of said integrated circuit to an input node of said noise measuring circuit; a signal conversion amplifier circuit converting voltage-input to current-output which input is an output of said source follower; and a current readout circuit for reading out an output current of said signal conversion amplifier circuit.
10. The semiconductor integrated circuit according to claim 9 , wherein each of said noise measuring circuits includes a select circuit which functions to activate each of said measuring circuit selectively.
11. The semiconductor integrated circuit according to claim 9 , wherein each of said noise measuring circuits further comprises a sampling switch circuit to an output node of said source follower.
12. The semiconductor integrated circuit according to claim 9 , wherein said current readout circuit of each of the noise measuring circuits is commonly shared.
13. An evaluation method and an adjustment method of a design CAD tool for the semiconductor integrated circuit according to claim 1 , wherein an analysis model evaluation or a parameter adjustment is performed based on actually measured noise data measured from said distributed arrangement positions of said noise measuring circuits.
14. The evaluation method and an adjustment method of a design CAD tool for the semiconductor integrated circuit according to claim 13 , wherein the analysis model evaluation is a power supply current analysis model for said design CAD tool for said semiconductor integrated circuit.
15. The evaluation method and an adjustment method of a design CAD tool for the semiconductor integrated circuit according to claim 13 , wherein the parameter adjustment is an impedance coefficient.
16. A diagnosis analysis method for a semiconductor integrated circuit, comprising: performing a malfunction diagnosis, an error analysis, a malfunction prediction, and an error prediction of said semiconductor integrated circuit based on an actual noise data obtained from said integrated circuit wherein said noise measuring circuits according to claim 9 are embedded in said integrated circuit.
17. An evaluation method and an adjustment method of a design CAD tool for the semiconductor integrated circuit, wherein an analysis model evaluation or a parameter adjustment is performed based on actually measured noise data measured from said distributed arrangement positions of said noise measuring circuits according to claim 9 .
18. A manufacturing process of a semiconductor integrated circuit including a sequential process for a designing process, a manufacturing process, and a testing (evaluating) process for said semiconductor integrated circuit wherein: said manufacturing process comprises a step for embedding noise measuring circuits according to claim 9 into distributed arrangement positions in said semiconductor integrated circuit; and said testing process comprises a step for measuring and evaluating said power supply noise waveform, ground level noise waveform, and a spatial distribution data by said noise measuring circuit.
19. The manufacturing process according to claim 18 , wherein said noise measuring circuits are automatically embedded into said positions of said integrated circuit by applying a standard cell base automatic wire layout designing method.
20. The manufacturing process according to claim 18 , wherein a built-in self test is performed by correlating a select logic of said noise measuring circuit to a test mode (a test pattern) logic of said integrated circuit.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 20, 2004
February 23, 2010
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