By providing additional etch stop layers and/or etch protection layers, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. Consequently, conductive line erosion and/or penetration into extension regions may be significantly reduced, thereby improving the reliability and performance of corresponding semiconductor devices.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method, comprising: forming an etch stop layer above a circuit element having a conductive line and an active semiconductor region, said etch stop layer covering an area that substantially corresponds to a contact opening to be formed to connect said conductive line and said active semiconductor region, wherein forming said etch stop layer comprises forming a mask layer for defining an opening above said circuit element, said opening having dimensions substantially corresponding to said contact opening, forming said etch stop layer in said opening and on said mask layer, and removing said mask layer; forming an interlayer dielectric material above said circuit element and said etch stop layer; forming said contact opening in said interlayer dielectric material by an etch process using said etch stop layer as an etch stop; and filling said contact opening with a conductive material.
2. The method of claim 1 , wherein forming said etch stop layer comprises depositing a dielectric material above said circuit element prior to depositing said interlayer dielectric material, said dielectric material of said etch stop layer having a high etch selectivity to at least a lower portion of said interlayer dielectric material.
3. The method of claim 2 , wherein depositing said interlayer dielectric material comprises depositing a contact etch stop layer on said etch stop layer and depositing an interlayer dielectric layer on said contact etch stop layer.
4. The method of claim 3 , wherein forming said contact opening comprises etching said interlayer dielectric layer using said contact etch stop layer as an upper etch stop, etching through said contact etch stop layer using said etch stop layer as said etch stop.
5. The method of claim 1 , wherein said mask layer is comprised of photoresist.
6. The method of claim 1 , wherein forming said etch stop layer comprises depositing a conductive etch stop material.
7. The method of claim 1 , wherein forming said etch stop layer comprises depositing an insulating material and removing said insulating material prior to filling said contact opening with said conductive material.
8. The method of claim 7 , further comprising forming at least one standard contact opening in said interlayer dielectric material together with said contact opening in a common process sequence.
9. The method of claim 1 , further comprising forming at least one sidewall spacer adjacent to said conductive line and using said at least one sidewall spacer to form said active semiconductor region by ion implantation prior to depositing said etch stop material.
10. The method of claim 1 , further comprising: forming an etch protection layer on sidewalls of said conductive line wherein said etch protection layer protects the sidewalls of said conductive line during the forming of said contact opening.
11. The method of claim 10 , wherein said etch stop layer is formed after forming said etch protection layer.
12. The method of claim 11 , wherein said etch stop layer is comprised of a conductive material.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 22, 2006
March 16, 2010
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