A system and method integrates signal filters in a multiband transceiver. A preferred embodiment comprises an amplifier with a first tunable capacitor coupled to a signal input and a tunable filter. The tunable filter comprises an input stage with a first pair of inductors arranged in a dipole configuration and a second tunable capacitor coupled in parallel to the first pair of inductors and an output stage inductively coupled to the input stage, the output stage includes a second pair of inductors also arranged in a dipole configuration and a third tunable capacitor coupled in parallel to the second pair of inductors. The inductors are realized using bond wire or any other high Q material. The first tunable capacitor, the second tunable capacitor, and the third tunable capacitor can be tuned using a master-slave tuning configuration to adjust the operating frequency of the amplifier and the tunable filter to enable frequency band compatibility with multiple communications protocols.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A circuit comprising: an amplifier coupled to a signal input, the amplifier to amplify a signal provided by the signal input to a specified level, the amplifier comprising a first tunable capacitor, wherein the first tunable capacitor is tuned by a reference oscillator, and wherein the first tunable capacitor is configured to tune a matching network coupled to the signal input to meet specified return loss requirements; a tunable inductor-capacitor (LC) filter having an input coupled to an output of the amplifier and an output coupled to a mixer, the tunable LC filter comprising: an input stage comprising: a first pair of inductors arranged in a dipole configuration, each inductor created from a high Q conductive material; a second tunable capacitor coupled in parallel to the first pair of inductors, the second tunable capacitor to adjust the frequency response of the input stage; and an output stage inductively coupled to the input stage, the output stage comprising: a second pair of inductors arranged in a dipole configuration, each inductor created from a high Q conductive material; and a third tunable capacitor coupled in parallel to the second pair of inductors, the third tunable capacitor to adjust the frequency response of the output stage.
2. The circuit of claim 1 , wherein the output stage of the tunable LC filter further comprises a Q enhance and tune (QET) circuit coupled in parallel to the second pair of inductors, the QET circuit to permit adjustments to a quality factor (Q) of the tunable LC filter by providing a negative resistance.
3. The circuit of claim 2 , wherein the QET circuit comprises a pair of cross-coupled transistors, wherein a control terminal of a first transistor is coupled to a first terminal of a second transistor, wherein a control terminal of the second transistor is coupled to a first terminal of the first transistor, and wherein a second terminal of the first transistor and a second terminal of the second transistor is coupled to electrical ground.
4. The circuit of claim 1 , wherein the first tunable capacitor, the second tunable capacitor, and the third tunable capacitor are tuned by the reference oscillator.
5. The circuit of claim 4 , wherein the reference oscillator comprises a phased-lock loop (PLL) oscillator used in a digital controlled oscillator (DCO).
6. The circuit of claim I, wherein the high Q conductive material comprises bond wire.
7. The circuit of claim 1 , wherein the high Q conductive material comprises bond wire, and wherein the high Q conductive material is placed over input/output pads formed onto a semiconductor substrate to create inductors.
8. The circuit of claim 1 , wherein the high Q conductive material comprises bond wire, and wherein the high Q conductive material is placed onto a substrate and a semiconductor substrate containing integrated circuitry is placed on top of the substrate with the high Q conductive material to create inductors.
9. The circuit of claim 1 , wherein the signal input is unbalanced, wherein the amplifier comprises a third transistor having a control terminal coupled to the signal input and a fourth transistor coupled in between an output terminal of the third transistor and the input stage of the tunable LC filter, the fourth transistor having a control terminal coupled to AC ground.
10. The circuit of claim 1 , wherein the signal input is balanced, wherein the amplifier comprises two pair of transistors, a first pair comprising a fifth transistor having a control terminal coupled to the signal input and a sixth transistor coupled in between an output terminal of the fifth transistor and the input stage of the tunable LC filter and a second pair comprising a seventh transistor having a control terminal coupled to the signal input and an eighth transistor coupled in between an output terminal of the seventh transistor and the input stage of the tunable LC filter, the sixth transistor and the eight transistor having control terminals coupled to AC ground.
11. The circuit of claim 10 , wherein the input stage further comprises a Q enhance and tune (QET) circuit coupled in parallel to the first pair of inductors, the QET circuit to permit adjustments to the Q of the tunable LC filter.
12. An integrated circuit for a multi-standard wireless communications device, the integrated circuit comprising: a front-end circuit, the front-end circuit having an input coupled to a matching network, the matching network being coupled to a signal input, wherein the signal input provides signals compliant to one or more communications standards, the front-end circuit comprising: an amplifier coupled to the matching network, the amplifier to amplify a signal provided by the matching network to a specified level, wherein the amplifier comprises a first tunable capacitor, wherein the first tunable capacitor is tuned by the reference oscillator, and wherein the first tunable capacitor is configured to tune a matching network coupled to the signal input to meet specified return loss requirements; a tunable LC filter having an input coupled to an output of the amplifier and an output coupled to a mixer, the tunable LC filter comprising: an input stage comprising: a first pair of inductors arranged in a dipole configuration, each inductor created from a high Q conductive material; a second tunable capacitor coupled in parallel to the first pair of inductors, the second tunable capacitor to adjust the frequency response of the input stage; an output stage inductively coupled to the input stage, the output stage comprising: a second pair of inductors arranged in a dipole configuration, each inductor created from a high Q conductive material; a third tunable capacitor coupled in parallel to the second pair of inductors, the third tunable capacitor to adjust the frequency response of the output stage; and the integrated circuit further comprising a digital processing circuit coupled to the front-end circuit, the digital processing circuit being configured to decode a digital representation of a signal provided by the front-end circuit into data.
13. The integrated circuit of claim 12 further comprising a second front-end circuit, the second front-end circuit having an input coupled to a second matching network and the second matching network is coupled to a second signal input, wherein the second signal input provides signals compliant to one or more communications standards, the second front-end circuit comprising: a second amplifier coupled to the second matching network, the second amplifier to amplify a signal provided by the second matching network to a specified level; and a second mixer coupled to an output of the second amplifier, wherein the second mixer is configured to down convert the output of the second amplifier to an internal frequency signal.
14. The integrated circuit of claim 12 , wherein the high Q conductive material is bond wire.
15. The integrated circuit of claim 12 , wherein the signals provided by the signal input to the front-end circuit are grouped based upon a frequency band used by each communications standard present in the signals.
16. The integrated circuit of claim 12 further comprising a third front-end circuit, the third front-end circuit having an input coupled to a third matching network and the third matching network is coupled to a third signal input, wherein the third signal provides signals compliant to one or more communications standards, the third front-end circuit comprising: a third amplifier coupled to the third matching network, the third amplifier to amplify a signal provided by the signal input to a specified level; an off-chip circuit coupled to the third amplifier, wherein the off-chip circuit is not integrated onto the integrated circuit, the off-chip circuit comprising: a fourth matching network coupled to the third amplifier, wherein the fourth matching network is configured to minimize signal loss due to impedance mismatch; a filter coupled to the fourth matching network, the filter is configured to separate signals located closely in frequency; a fifth matching network coupled to the filter, wherein the fifth matching network is configured to minimize signal loss due to impedance mismatch; and a third mixer coupled to the off-chip circuit, wherein the third mixer is integrated in the integrated circuit, wherein the third mixer is configured to down convert the output of the second amplifier to an internal frequency.
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January 24, 2005
March 16, 2010
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