A method for the computer-aided ascertainment of a clock tree structure which couples a clock generation unit to a multiplicity of switching elements ascertains first switching elements from the multiplicity of switching elements, the first switching elements infringing a prescribed, first time-based switching criterion. In further method steps, the first switching elements are linked to the clock generation unit, and a first buffer element is inserted between the clock generation unit and the first switching elements. An integrated semiconductor circuit has a multiplicity of switching elements which are coupled to a clock generation unit via a clock tree structure. It also has a multiplicity of first switching elements which infringe a time-based switching criterion, which multiplicity is ascertained from the multiplicity of switching elements. A buffer element is inserted into the clock tree structure between the clock generation unit and the first switching elements.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A computer-readable storage medium which stores a computer program for ascertaining a clock tree structure and which, when executed by a processor, comprises the following steps: determining setup conditions and hold conditions on a multiplicity of switching elements, selecting first switching elements from the multiplicity of switching elements, the selecting based on whether the first switching elements infringe a prescribed, first time-based switching criterion, the first time-based switching criterion being based on the determined setup conditions and/or the determined hold conditions; linking the first switching elements to a clock generation unit, and inserting a first buffer element between the clock generation unit and the first switching elements, wherein a time delay of a portion of the clock tree structure common to the first switching elements is increased.
2. The computer-readable storage medium according to claim 1 , wherein the first switching elements are selected such that at least some of them are connected to one another via direct data links.
3. The computer-readable storage medium according to claim 1 , wherein the first switching elements are selected such that a physical distance between each pair of first switching elements is shorter than a maximum prescribed distance.
4. The computer-readable storage medium according to claim 1 , wherein the first switching elements are selected such that the number of first switching elements is smaller than a maximum prescribed number.
5. The computer-readable storage medium according to claim 1 , wherein the computer program, when executed by the processor, further comprises the following steps: selecting second switching elements which infringe a prescribed, second time-based switching criterion from the multiplicity of switching elements, linking the second switching elements to the clock generation unit, and inserting a second buffer element between the clock generation unit and the second switching elements.
6. The computer-readable storage medium according to claim 5 , wherein the second switching elements are selected from the set of switching elements without the first switching elements.
7. The computer-readable storage medium according to claim 5 , wherein the second switching elements are selected from the set of first switching elements, and the second buffer element is inserted between the first buffer element and the second switching elements.
8. The computer-readable storage medium according to claim 5 , wherein the second time-based switching criterion is selected taking into account hold conditions and/or setup conditions on the switching elements.
9. The computer-readable storage medium according to claim 5 , wherein the computer program, when executed by the processor, further comprises the following steps: selecting third elements meeting the first time-based switching criterion and the second time-based switching criterion from the multiplicity of switching elements, linking the third switching elements to the clock generation unit, and inserting a third buffer element between the clock generation unit and the third switching elements.
10. The computer-readable storage medium according to claim 9 , wherein the computer program, when executed by the processor, further comprises the following step: shifting a clock signal arrival time on at least one third switching element by inserting at least one delay element between the third buffer element and the third switching element in order to minimize the number of third switching elements changing a switching state at the same time.
11. The computer-readable storage medium according to claim 1 , wherein the computer program, when executed by the processor, further comprises creating a layout for a semiconductor circuit, in which the clock tree structure is ascertained.
12. An apparatus for ascertaining a clock tree structure comprising the computer-readable storage medium of claim 1 .
13. An integrated semiconductor circuit comprising: a multiplicity of switching elements, a plurality of first switching elements selected from the multiplicity of switching elements that infringe a time-based switching criterion, the time-based switching criterion based on measured setup and hold conditions on the multiplicity of switching elements, and a buffer element which is inserted in a clock tree structure coupled between a clock generation unit and the first switching elements, wherein a time delay of a portion of the clock tree structure common to the first switching elements is increased.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 13, 2005
April 27, 2010
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.