An apparatus and method for providing external electrostatic discharge (ESD) protection to a semiconductor device, which may or may not include its own ESD protection, are provided. An ESD structure may be associated with each interconnect, either individually or shared between two or more interconnects. Each interconnect includes a contact tip for establishing a temporary electrical connection with a bond pad of the semiconductor device and a contact pad for electrically interfacing the bond pad with external burn-in and/or test equipment. The ESD structure may be implemented, for example, as a fusible element or a shunting element, such as a pair of diodes, a diode-resistor network, or a pair of transistors. The interconnect may be employed as part of an insert including a plurality of interconnects that provides ESD protection to a plurality of integrated circuits of at least one semiconductor device.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for protecting a separate semiconductor device from at least one electrostatic discharge event during testing of the separate semiconductor device, the method comprising: electrically connecting testing circuitry to an insert of configured to establish electrical communication with the separate semiconductor device, the insert consisting of: a bulk semiconductor substrate comprising a full or partial wafer; contact structures carried by the bulk semiconductor substrate; at least one conductor carried by the bulk semiconductor substrate and in communication with a pair of the contact structures; and at least one electrostatic discharge structure in communication with the at least one conductor, the at least one electrostatic discharge structure including: a first resistive element located between a contact pad of the insert and a node; and a second resistive element located between the node and at least one test contact of the insert; assembling the separate semiconductor device in superimposed relation over the insert with at least one bond pad of the separate semiconductor device aligned with a corresponding contact structure of the insert and electrically connecting the at least one bond pad of the separate semiconductor device to the corresponding contact structure of the insert; applying at least one test signal through the insert, including through an electrostatic discharge structure carried by the insert, to the separate semiconductor device; and shunting at least one electrostatic discharge event: through the first resistive element, which limits a peak current; and from the first resistive element into a first diode that communicates with a V DD voltage if a magnitude of a voltage of the at least one electrostatic discharge event exceeds a predetermined maximum positive voltage threshold or into a second diode that communicates with a V SS voltage if a magnitude of the at least one electrostatic discharge event exceeds a predetermined maximum negative voltage threshold; and conveying current within a range defined by the predetermined maximum positive voltage threshold and the predetermined maximum negative voltage threshold through the first resistive element, to the second resistive element, and through the second resistive element for application to a circuit of the separate semiconductor device.
2. The method of claim 1 , wherein electrically connecting the separate semiconductor device comprises placing the at least one bond pad of the separate semiconductor device against the corresponding contact structure of the insert, with the corresponding contact structure comprising a contact tip.
3. The method of claim 2 , wherein, during placing of the at least one bond pad of the separate semiconductor device against the contact tip of the insert, a configuration of at least one of the at least one bond pad and the contact tip facilitates self-alignment of the at least one bond pad with the contact tip.
4. The method of claim 2 , wherein placing the at least one bond pad of the separate semiconductor device against the contact tip of the insert includes self-alignment of the separate semiconductor device with the insert.
5. The method of claim 1 , wherein electrically connecting the separate semiconductor device comprises placing a plurality of semiconductor devices adjacent to the insert.
6. The method of claim 1 , wherein shunting the at least one electrostatic discharge event includes shunting the excess voltage through the first diode if a voltage of the at least one electrostatic discharge event is at least 0.7 V more than the V DD voltage.
7. The method of claim 1 , wherein shunting the at least one electrostatic discharge event includes shunting the excess voltage through the second resistor resistive element and into the second diode if a voltage of the at least one electrostatic discharge event is at least 0.7 V less than the V SS voltage.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 20, 2004
May 4, 2010
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