Patentable/Patents/US-7709863
US-7709863

Solid state imaging device

PublishedMay 4, 2010
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A solid state imaging device in which γ characteristic is obtained and enlargement of dynamic range is provided. The solid state imaging device of the present invention includes a vertical overflow function and has a feature in which potential of a semiconductor substrate is changed from a high potential to a low potential in a stepwise manner during a period from an exposure start to an exposure end.

Patent Claims
4 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A solid state imaging device having a vertical overflow function, the solid state imaging device comprising: a semiconductor substrate; a p-type well region formed on the substrate; a photosensor portion formed on the p-type well region, the photosensor portion including an n-type semiconductor region and a p-type charge accumulation region formed on the surface of the n-type semiconductor region; and a substrate voltage value controller configured to change a potential applied to the semiconductor substrate from a high potential to a low potential in a stepwise manner during a period from an exposure start to an exposure end, thereby increasing a potential barrier of the p-type well region from a low state to a high state in a corresponding stepwise manner.

2

2. A solid state imaging device according to claim 1 , wherein an amount of a saturation current is controlled so as to become larger in a stepwise manner depending on the stepwise change of said semiconductor substrate potential.

3

3. A solid state imaging device according to claim 1 , wherein the substrate voltage value controller is configured to change the potential in a horizontal blanking period.

4

4. A solid state imaging device according to claim 1 , wherein the semiconductor substrate is an n-type substrate, and the solid state imaging device further comprises an n-type high impurity concentration region formed on the rear surface side of the semiconductor substrate.

Classification Codes (CPC)

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Patent Metadata

Filing Date

October 4, 2005

Publication Date

May 4, 2010

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