Flash memory device and method of testing a flash memory device

1. A flash memory device, comprising: a fuse cell array configured to store a first trim code, the flash fuse cell array comprising a plurality of nonvolatile fuse cells; a trim code processor configured to generate a second trim code based on the first trim code provided by the fuse cell array and a voltage control code; a flash memory array comprising a plurality of flash memory cells; and a regulator configured to generate a high voltage in response to the second trim code and to provide the high voltage to the flash memory array, the high voltage varying according to erase, program and read operations of the flash memory cells, wherein the trim code processor comprises: a first register configured to store the first trim code; a second register configured to store the voltage control code; and a calculator configured to generate the second trim code by adding or subtracting the voltage control code to or from the first trim code.

2. The flash memory device of claim 1 , wherein the voltage control code is extracted from a test command provided to the flash memory device to control testing of the flash memory device, the voltage control code including information about a displacement value of the high voltage level.

3. The flash memory device of claim 2 , wherein the calculator adds or subtracts the voltage control code to or from the first trim code in response to the test command.

4. A method of testing a flash memory device, the flash memory device comprising a flash fuse cell array, having nonvolatile fuse cells, and a regulator for generating a high voltage based on information output from the flash fuse cell array, the method comprising: setting a first trim code in the flash fuse cell array, the first trim code for correcting a level of the high voltage generated by the regulator; generating a second trim code based on the first trim code and a voltage control code; generating the high voltage having a corrected level in response to the second trim code; receiving a test command; extracting the voltage control code from the test command to control testing of the flash memory device, the voltage control code representing information about a displacement value of the high voltage level, wherein generating the second trim code comprises adding or subtracting the voltage control code to or from the first trim code, according to the test command.

5. The method of claim 4 , further comprising: providing the voltage control code to at least one other flash memory device being simultaneously tested.

6. The method of claim 4 , further comprising: maintaining the first trim code during the testing.

7. An electronic circuit, comprising: a flash fuse cell array configured to store a first trim code, the fuse cell array comprising nonvolatile fuse cells; a trim code processor configured to generate a second trim code based on the first trim code and a voltage control code; and a regulator configured to generate a high voltage in response to the second trim codes, wherein the trim code processor comprises: a first register configured to store the first trim code received from the flash fuse cell array; a second register configured to store the voltage control code; and a calculator configured to calculate the second trim code based on the first trim code and the voltage control code.

8. The electronic circuit of claim 7 , wherein the voltage control code is extracted from a test command received by the trim code processor, the voltage control code indicating a displacement value of the high voltage level.

9. The electronic circuit of claim 8 , wherein the calculator is configured to one of add or subtract the voltage control code to or from the first trim code in response to the test command to calculate the second trim code.

10. The electronic circuit of claim 7 , wherein first trim code stored in the flash fuse cell array is maintained while the high voltage is generated in response to the second trim code.