A silicon epitaxial layer 2 is grown in vapor phase on a silicon single crystal substrate 1 manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 Ω·cm or below, oxygen precipitation nuclei 11 are formed in the silicon single crystal substrate 1, by carrying out annealing at 450° C. to 750° C., in an oxidizing atmosphere, for a duration of time allowing formation of a silicon oxide film only to as thick as 2 nm or below on the silicon epitaxial layer 2 as a result of the annealing, and thus-formed silicon oxide film 3 is etched as the first cleaning after the low-temperature annealing, using a cleaning solution. By this process, the final residual thickness of the silicon oxide film can be suppressed only to a level equivalent to native oxide film, without relying upon the hydrofluoric acid cleaning.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a silicon epitaxial wafer comprising: a vapor phase growth step allowing a silicon epitaxial layer to grow in vapor phase on a silicon single crystal substrate manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 Ω·cm or below; a low-temperature annealing step forming, following the vapor phase growth step, oxygen precipitation nuclei in the silicon single crystal substrate, by carrying out annealing at 450° C. to 750° C., both ends inclusive, in an oxidizing atmosphere for a duration of time allowing formation of a silicon oxide film only to as thick as 2 nm or below on the silicon epitaxial layer as a result of the annealing; and a cleaning step, as the first cleaning step after the low-temperature annealing step, etching the silicon oxide film formed in the low-temperature annealing step, using a cleaning solution composed of a mixed solution of ammonia, hydrogen peroxide and water, all of these steps being executed in this order, wherein a thickness of the silicon oxide film after the cleaning step is smaller than the thickness attained after the annealing step, and is adjusted to 1 nm or above.
2. The method of manufacturing a silicon epitaxial wafer claimed in claim 1 , wherein particle count on the silicon epitaxial layer after execution of the cleaning step is smaller than the particle count before the cleaning step.
3. The method of manufacturing a silicon epitaxial wafer claimed in claim 2 , wherein SC-1 cleaning solution is used as the cleaning solution.
4. The method of manufacturing a silicon epitaxial wafer claimed in claim 1 , wherein SC-1 cleaning solution is used as the cleaning solution.
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August 3, 2005
May 11, 2010
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