A laser tracking processor is provided for integrating measured target-reflection signals used in directional control. The integration is performed to distinguish pulses reflected from the target against a noise background. The processor includes an optical detector, an accumulator, a correlator, a phase-lock loop and an integrator array. The optical detector receives the measured signals distributed among several guidance channels. The accumulator sums the measured signals as a combined signal for all the channels. The correlator temporally identifies an event that occurs to indicate a target-reflection pulse within the combined signal. The phase-lock loop synchronizes the event with a clock reference to produce a pulse window within which to search the combined signal for the pulses. The integrator array superimposes the measured signals within the pulse window for each channel to produce channel-specific integrated pulse signals. The processor can further include a sum integrator, a noise comparator and a reset trigger. The sum integrator superimposes a temporal sequence of combined signals from the accumulator as sum integration signals. The noise comparator determines whether the sum integrated signals exceed a noise threshold to set a detection satisfaction condition. The reset trigger initializes the temporal sequence of the integrator array and the sum integrator in response to the detection satisfaction condition, so that as the processor approaches the target, the guidance system can receive updates from the measured signals after becoming distinguishable above the noise.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A laser tracking processor for integrating measured target-reflection signals for directional control, said processor comprising: an optical detector that receives the measured signals distributed among a plurality of guidance channels; an accumulator that sums the measured signals as a combined signal for all said channels; a correlator that temporally identifies event occurrence of a target-reflection pulse within said combined signal; a phase-lock loop that synchronizes said event occurrence with a clock reference as a pulse window; and an integrator array that superimposes the measured signals within said pulse window for each said channel to produce channel-specific integrated pulse signals; and a sum integrator that superimposes a temporal sequence of combined signals from said accumulator as sum integration signals; a noise comparator that determines whether said sum integrated signals exceed a noise threshold to set a detection satisfaction Condition; and a reset trigger that initializes said temporal sequence of said integrator array and said sum integrator in response to said detection satisfaction condition.
2. The processor according to claim 1 , further comprising: a matched filter that isolates received signals within specified frequency ranges for receipt into said correlator as a filtered signal.
3. The processor according to claim 2 , wherein said matched filter provides a shifting definite integral of said combined signal, as expressed by: S filter — output (t)∫ −T S filter — input (τ)·dτ, where S is a signal amplitude, t is a shifting sample time, τ is an integration time, and T is an interval between consecutive pulses.
4. The processor according to claim 2 , wherein said comparator further comprises: a phase selector that sequences a plurality of phases within said combined signal, each phase of said plurality of phases representing a finite temporal period; a plurality of integrators corresponding respectively to said plurality of phases, such that each integrator superimposes said filtered signal within each respective phase as an integrated phase signal; a plurality of thresholds corresponding respectively to said plurality of integrators, such that each threshold compares said integrated phase signal against a phase threshold to determine a phase satisfaction condition; and a logic gate that indicates a threshold-satisfying phase among said plurality of phases in response to at least one phase satisfaction condition.
5. The processor according to claim 1 , wherein said comparator further comprises: a phase selector that sequences a plurality of phases within said combined signal, each phase of said plurality of phases representing a finite temporal period; a plurality of integrators corresponding respectively to said plurality of phases, such that each integrator superimposes said combined signal within each respective phase as an integrated phase signal; a plurality of thresholds corresponding respectively to said plurality of integrators, such that each threshold compares said integrated phase signal against a phase threshold to determine a phase satisfaction condition; and a logic gate that indicates a threshold-satisfying phase among said plurality of phases in response to at least one phase satisfaction condition.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 25, 2008
May 11, 2010
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