According to one embodiment of the present invention, a memory cell array comprises a plurality of voids, the spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit comprising a memory cell array comprising a plurality of voids, spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids, wherein the memory cell array comprises a solid electrolyte random access memory cell array comprising a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and wherein at least a part of at least one void is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and at least one dielectric layer that is disposed above the solid electrolyte layer.
2. The integrated circuit according to claim 1 , wherein at least a part of at least one void is filled with compressible material or material having a negative thermal expansion coefficient.
3. The integrated circuit according to claim 2 , wherein the compressible material comprises a nanoporous material.
4. The integrated circuit according to claim 1 , wherein the memory cell array comprises a resistive memory cell array.
5. The integrated circuit according to claim 1 , wherein the memory cell array comprises a non-volatile memory cell array.
6. The integrated circuit according to claim 1 , wherein the memory cell array comprises an active material layer, at least a part of at least one void being located within the active material layer.
7. The integrated circuit according to claim 6 , wherein all voids are located within the active material layer.
8. The integrated circuit according to claim 1 , wherein all voids are located within at least one dielectric material layer.
9. The integrated circuit according to claim 6 , wherein all voids are located within at least one dielectric material layer that is disposed above an active material layer and/or an electrode layer that is disposed above the active material layer.
10. The integrated circuit according to claim 2 , wherein at least part of at least one void is filled with a material having a negative thermal expansion coefficient, the material comprising a compound.
11. The integrated circuit according to claim 10 , wherein the material having a negative thermal expansion coefficient comprises ZrW 2 O 8 .
12. An integrated circuit comprising a memory cell array comprising a plurality of mechanical stress compensation areas, each stress compensation area comprising compressible material or material having a negative thermal expansion coefficient, spatial positions and dimensions of the stress compensation areas being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the stress compensation areas, wherein the memory cell array comprises a programmable metallization cell array, wherein the memory cell array comprises a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer that is positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and wherein at least a part of at least one stress compensation area is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and at least one dielectric layer that is disposed above the solid electrolyte layer.
13. The integrated circuit according to claim 12 , wherein each stress area comprises a compressible material, the compressible material comprising a nanoporous material.
14. The integrated circuit according to claim 12 , wherein the memory cell array comprises a resistive memory cell array.
15. The integrated circuit according to claim 12 , wherein the memory cell array comprises a non-volatile memory cell array.
16. The integrated circuit according to claim 12 , wherein at least one stress compensation area comprises a trench structure, the trench structure being at least partially filled with the compressible material or the material having a negative thermal expansion coefficient.
17. The integrated circuit according to claim 12 , wherein the memory cell array comprises an active material layer, at least a part of at least one stress compensation area being located within the active material layer.
18. The integrated circuit according to claim 17 , wherein all stress compensation areas are located within the active material layer.
19. The integrated circuit according to claim 17 , wherein all stress compensation areas are located within a dielectric material layer that is disposed above the active material layer.
20. The integrated circuit according to claim 12 , wherein the memory cell array comprises a phase changing memory cell array.
21. The integrated circuit according to claim 12 , further comprising a plurality of voids, spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids.
22. The integrated circuit according to claim 12 , wherein each stress compensation area comprises ZrW.sub.2O.sub.8.
23. A memory cell array comprising a plurality of voids, spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids, wherein the memory cell array comprises a solid electrolyte random access memory cell array comprising a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and wherein at least a part of at least one void is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and the at least one dielectric layer that is disposed above the solid electrolyte layer.
24. A memory cell array comprising a plurality of mechanical stress compensation areas, each stress compensation area comprising compressible material or material having a negative thermal expansion coefficient; and spatial positions and dimensions of the stress compensation areas being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the stress compensation areas, wherein the memory cell array comprises a programmable metallization cell array, wherein the memory cell array comprises a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer that is positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and wherein at least a part of at least one stress compensation area is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and at least one dielectric layer that is disposed above the solid electrolyte layer.
25. A memory module comprising at least one memory device comprising a memory cell array that comprises a plurality of voids, spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids, wherein the memory module comprises a solid electrolyte random access memory cell array comprising a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and wherein at least a part of at least one void is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and at least one dielectric layer that is disposed above the solid electrolyte layer.
26. A memory module comprising at least one memory device comprising a memory cell array that comprises a plurality of mechanical stress compensation areas, each stress compensation area comprising compressible material or material having a negative thermal expansion coefficient; and spatial positions and dimensions of the stress compensation areas being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the stress compensation areas, wherein the memory module comprises a programmable metallization cell array, wherein the memory cell array comprises a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer that is positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and wherein at least a part of at least one stress compensation area is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and at least one dielectric layer that is disposed above the solid electrolyte layer.
27. The memory module according to claim 26 , wherein the memory module is stackable.
28. A semiconductor device comprising a plurality of voids, spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the device is at least partly compensated by the voids, wherein the semiconductor device comprises a solid electrolyte random access memory cell array comprising a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and wherein at least a part of at least one void is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and at least one dielectric layer that is disposed above the solid electrolyte layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 16, 2007
June 8, 2010
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