Semiconductor memory device and a data write and read method thereof

1. A semiconductor memory device comprising: a write data controller writing data received with an address to a memory cell corresponding to the address and storing the data in a data register in parallel with writing the data to the memory cell according to a synchronous operation mode signal and an asynchronous operation mode signal; an address controller decoding and storing the address in an address register according to the synchronous operation mode signal and the asynchronous operation mode signal; and a read data controller outputting data from the memory cell corresponding to an address received with a data read command if the received address is different from the address stored in the address register, and outputting the data stored in the data register if the received address is equal to the address stored in the address register, wherein the write data controller comprises: a synchronous operation write circuit receiving the data to be written in response to the synchronous operation mode signal and writing the data to the memory cell in response to a first control signal; and an asynchronous operation write circuit receiving the data to be written in response to the asynchronous operation mode signal or the synchronous operation mode signal, storing the data to be written in the data register in response to the first control signal or a second control signal, and writing the data stored in the data register to the memory cell in response to a third control signal.

2. The semiconductor memory device of claim 1 , wherein the first control signal is activated in response to a write enable signal in the synchronous operation mode, the second control signal is activated in response to a data read command in the asynchronous operation mode, and the third control signal is activated in response to a data write command in the asynchronous operation mode.

3. The semiconductor memory device of claim 1 , wherein the synchronous operation write circuit comprises: a first switch receiving the data to be written in response to the synchronous operation mode signal; and a second switch transmitting or blocking the data output from the first switch to the memory cell in response to the first control signal, and the asynchronous operation write circuit comprises: a third switch receiving the data to be written in response to the asynchronous operation mode signal or the synchronous operation mode signal; a fourth switch transmitting or blocking the data output from the third switch in response to the first control signal or the second control signal; the data register storing the data output from the fourth switch; and a fifth switch transmitting or blocking the data stored in the data register in response to the third control signal.

4. The semiconductor memory device of claim 3 , wherein the synchronous operation write circuit further comprises a first write circuit for writing the data output from the second switch to the memory cell, and the asynchronous operation write circuit further comprises a second write circuit for writing the data output from the fifth switch to the memory cell.

5. The semiconductor memory device of claim 1 , wherein the write data controller further comprises a selector for selecting the data output from the synchronous operation write circuit or the asynchronous operation write circuit in response to the synchronous operation mode signal and the asynchronous operation mode signal, and applying the selected data to the memory cell.

6. The semiconductor memory device of claim 5 , wherein the selector comprises: a first logic gate outputting the data output from the first write circuit in response to the synchronous operation mode signal; a second logic gate outputting the data output from the second write circuit in response to the asynchronous operation mode signal; and a third logic gate receiving the output of the first logic gate and the second logic gate, performing a logic operation on the output of the first logic gate and the second logic gate and outputting a result of the logic operation to the memory cell.

7. The semiconductor memory device of claim 1 , wherein the address controller comprises: a synchronous operation address circuit receiving the address in response to the synchronous operation mode signal and transmitting or blocking the address in response to the first control signal; and an asynchronous operation address circuit receiving the address in response to the asynchronous operation mode signal or the synchronous operation mode signal, storing the address in the address register in response to the first control signal or the second control signal, outputting the address stored in the address register in response to the third control signal, and determining whether the address received with the data read command is equal to the address stored in the address register, and generating a bypass signal according to a result of the determination.

8. The semiconductor memory device of claim 7 , wherein the bypass signal has a first level if the address received with the data read command is equal to the address stored in the address register, and has a second level if the address received with the data read command is different from the address stored in the address register.

9. The semiconductor memory device of claim 7 , wherein the synchronous operation address circuit comprises: a first address switch receiving the address in response to the synchronous operation mode signal; and a second address switch transmitting or blocking the address in response to the first control signal, and the asynchronous operation address circuit comprises: a third address switch receiving the address in response to the asynchronous operation mode signal or the synchronous operation mode signal; a fourth address switch transmitting or blocking the address output from the third address switch in response to the first control signal or the second control signal; the address register storing the address output from the fourth address switch; a fifth address switch transmitting or blocking the address stored in the address register in response to the third control signal; and a comparator determining whether the address received with the data read command is equal to the address stored in the address register and generating the bypass signal according to a result of the determination.

10. The semiconductor memory device of claim 7 , wherein the read data controller comprises an output selector for selectively outputting one of the data stored in the data register and the data stored in the memory cell in response to the bypass signal, and the output selector selects the data stored in the memory cell if the bypass signal has the second level and selects the data stored in the data register if the bypass signal has the first level.

11. The semiconductor memory device of claim 1 , wherein the semiconductor memory device has a synchronous operation mode in which the semiconductor memory device operates in synchronization with a clock signal, and an asynchronous operation mode in which the semiconductor memory device does not operate in synchronization with the clock signal.

12. The semiconductor memory device of claim 1 , wherein the semiconductor memory device is a Pseudo Static Random Access Memory (PSRAM).

13. The semiconductor memory device of claim 1 , further comprising: a plurality of memory cells.

14. A semiconductor memory device comprising: a write data controller writing data received with an address to a memory cell corresponding to the address and storing the data in a data register in parallel with writing the data to the memory cell according to a synchronous operation mode signal and an asynchronous operation mode signal; an address controller decoding and storing the address in an address register according to the synchronous operation mode signal and the asynchronous operation mode signal; and a read data controller outputting data from the memory cell corresponding to an address received with a data read command if the received address is different from the address stored in the address register, and outputting the data stored in the data register if the received address is equal to the address stored in the address register, wherein the semiconductor memory device is a Pseudo Static Random Access Memory (PSRAM).