A method of forming an interconnection in a semiconductor device includes forming a first liner in a dielectric layer therein; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten filler from the semiconductor's exposed surface; selectively removing the first liner and tungsten filler in the via; wherein the selective removing results in the first liner and the tungsten filler being removed in an upper region of the via; forming a second liner in the upper region of the via and tungsten filler; selectively removing the second liner from the tungsten filler; forming a copper seed layer on top of the tungsten filler; depositing a copper filler on top of the copper seed layer; and performing chemical CMP to smooth out and remove the second liner and copper filler from the semiconductor's exposed surface.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming an interconnection in a semiconductor, the method comprising: forming a first liner on the sidewalls and bottom region of a via formed in a dielectric layer of the semiconductor; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten filler from the top of the semiconductor's exposed surface; selectively removing the first liner and tungsten filler in the via; wherein the selective removing results in the first liner and the tungsten filler being removed in an upper region of the via; forming a second liner on the sidewalls of the upper region of the via and on the upper surface of the tungsten filler; selectively removing the second liner from the upper surface of the tungsten filler; forming a copper seed layer on top of the tungsten filler and along the sidewalls of the upper region of the via; depositing a copper filler on top of the copper seed layer; and performing chemical mechanical planarization (CMP) to smooth out and remove the second liner and copper filler from the top of the semiconductor's exposed surface.
2. The method of claim 1 , wherein the first liner and the second liner comprise one or more of the following refractory materials: tantalum, tungsten, tantalum nitride, tungsten nitride, titanium, and titanium nitride.
3. The method of claim 1 , wherein the first liner comprises a layer of titanium and a layer of titanium nitride.
4. The method of claim 1 , wherein the first liner comprises a layer of titanium and a layer of tungsten nitride.
5. The method of claim 1 , wherein the second liner comprises a layer of tantalum and a layer of tantalum nitride.
6. The method of claim 1 , wherein the selective removing of the first liner and tungsten filler in the upper region of the via is performed by a dry or a wet etching process.
7. The method of claim 1 , wherein chemical vapor deposition is used to dispose the first and the second liners.
8. The method of claim 1 , wherein physical vapor deposition is used to dispose the first and second liners.
9. The method of claim 1 , wherein atomic layer deposition is used to dispose the first and the second liners.
10. The method of claim 1 , wherein selectively removing the second liner from the upper surface of the tungsten filler is conducted with a sputtering process in an inert gas.
11. The method of claim 1 , further comprising forming an anchor in the upper surface of the tungsten filler by a sputter etch during the selective removal of the second liner; wherein the anchor has downward angled walls that end in a flat surface; and wherein the anchor serves as an interface for the copper and tungsten filler.
12. The method of claim 11 , wherein the depth and shape of the anchor is modulated by the sputter etch conditions including one or more of: RF power, the nature and pressure of the inert gas, substrate bias, and sputtering time; wherein the depth is within a range of about 2 nm to about 20 nm into the tungsten filler; and wherein during the sputtering process, the second liner and the tungsten filler are re-deposited onto the sidewalls of the upper region of the via.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 29, 2007
June 15, 2010
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.