Well isolation trenches (WIT) for CMOS devices

1. A semiconductor structure, comprising: (a) a semiconductor substrate; (b) a P well, an N well, and an N band region in the semiconductor substrate, wherein the P well comprises a first shallow trench isolation (STI) region and a first doped region, and wherein the N well comprises a second STI region and a second doped region; and (c) a well isolation region sandwiched between and only in direct physical contact with the P well, the N well, the first doped region, the second doped region, and the N band region, wherein a the horizontal bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions, wherein the horizontal bottom surface of the well isolation region is only in contact with the N band region and the N well; wherein when going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function, wherein said well isolation region comprises vertical side surfaces formed entirely perpendicular to a horizontal top surface of said well isolation region and said horizontal bottom surface, and wherein each vertical side surface of said vertical side surfaces consists of a single planer surface.

2. The semiconductor structure of claim 1 , wherein the first and second STI regions comprise silicon dioxide.

3. The semiconductor structure of claim 1 , wherein a top surface of the well isolation region is essentially coplanar with top surfaces of the first and second STI regions.

4. The semiconductor structure of claim 1 , further comprising an N channel transistor on the P well; and a P channel transistor on the N well.

5. The semiconductor structure of claim 4 , wherein the N channel transistor and the P channel transistor are connected so as to form a CMOS device.

6. The semiconductor structure of claim 1 , wherein the N band is formed directly beneath the P well and in direct physical contact with the N well.

7. The semiconductor structure of claim 1 , wherein said well isolation region consists of a single uniform width.

8. The semiconductor structure of claim 1 , wherein each said vertical side surface does not comprise a slope.

9. The semiconductor structure of claim 1 , wherein the first STI region only extends through a top surface and into a portion of the P well, and wherein the second STI region only extends through a top surface and into a portion of the N well.

10. The semiconductor structure of claim 1 , wherein the P well further comprises a third doped region, a fourth doped region, a fifth doped region, and a third STI region, wherein the N well comprises a sixth doped region, a seventh doped region, an eighth doped region, and a fourth STI region, wherein the first STI region separates the third doped region from the fourth doped region, wherein the third STI region separates the fourth doped region from the fifth doped region, wherein the second STI region separates the sixth doped region from the seventh doped region, wherein the fourth STI region separates the seventh doped region from the eighth doped region, wherein the first doped region, the third doped region, the fifth doped region, and the seventh doped region each comprise N type dopants, and wherein the second doped region, the fourth doped region, the sixth doped region, and the eighth doped region each comprise P type dopants.

11. The semiconductor structure of claim 1 , wherein the N band region extends below a non-entire portion of the horizontal bottom surface of the well isolation region.

12. The semiconductor structure of claim 1 , wherein the N well region extends below a non-entire portion of the horizontal bottom surface of the well isolation region.