A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A charge pump system comprising: a charge pump including an output stage; and a plurality of boost circuits, one of said plurality of boost circuits selectively and successively boosting voltage on the input of the output stage of the charge pump and others of said plurality of boost circuits coupled to an output of the output stage and selectively and successively boosting voltage on the output of the output stage, each of the others of said plurality of boost circuits increasing the boost voltage on said output in response to a load on said output by said others of said plurality of boost circuits and in response to being selected, and becoming loadless on said output after said each of the others of said plurality of boost circuits has successively boosted a voltage on said output, said each of the plurality of boost circuits becoming loadless in response to said successive boosting, all of said others of said plurality of boost circuits being loadless on said output after all of said others of said plurality of boost circuits have been selected and have successively boosted the voltage on said output; wherein the plurality of boost circuits maintain a ratio of boost capacitance to overall output stage capacitance for each successive boost as each of the plurality of boost circuits becomes loadless.
2. The charge pump system of claim 1 wherein the boost circuits provide said boosting of voltage in a series of successively timed boosts.
3. The charge pump system of claim 1 wherein said boosting is in response to an address transition.
4. The charge pump system of claim 1 wherein said boosting is in response to an address transition and after switching of an address decoder.
5. The charge pump system of claim 1 wherein each boost circuit provides a boost in voltage as a function of capacitance values of capacitors included in the boost circuits.
6. A charge pump system of claim 1 wherein each boost circuit comprises a capacitor that, after being used to boost a voltage on a node, presents no load to a node coupled to said output of the output stage for a subsequent boost.
7. A charge pump system comprising: a charge pump including an output terminal for providing a voltage signal; and a plurality of boost circuits, said plurality of boost circuits coupled to the output terminal and selectively and successively boosting voltage on the output terminal of the charge pump during a first mode, each of the plurality of boost circuits increasing the boost voltage on the output terminal of the charge pump in response to a load on said output by others of the plurality of boost circuits and in response to being selected, each of the plurality of boost circuits becoming loadless on the output terminal after said each of the plurality of boost circuits has been selected and has successively boosted said voltage on the output terminal, said each of the plurality of boost circuits becoming loadless in response to said successive boosting, said charge pump providing a voltage on the output terminal in a second mode, all of said plurality of boost circuits being loadless on said output terminal after all of said plurality of boost circuits have been selected and have successively boosted the voltage on said output; wherein the plurality of boost circuits maintain a ratio of boost capacitance to overall output terminal capacitive load for each successive boost as each of the plurality of boost circuits becomes loadless.
8. The charge pump system of claim 7 , wherein each boost circuit provides said boosting of voltage in a series of successively timed boosts.
9. The charge pump system of claim 8 , wherein the successive boosting is in response to address transition detection.
10. The charge pump system of claim 9 wherein said boosting is in response to an address transition and after switching of an address decoder.
11. The charge pump system of claim 7 , wherein each boost circuit comprises a capacitor.
12. The charge pump system of claim 11 , wherein the capacitor of a boost circuit that boosts the voltage has a capacitance such that the ratio of the capacitors of the boost circuits not previously boosting voltage maintain a predetermined ratio.
13. An on-chip boost circuit comprising: a plurality of boost circuits coupled to a voltage node, at least one of said plurality of boost circuits selectively, successively and loadlessly boosting voltage on a voltage node, each of the plurality of boost circuits increasing the boost voltage on the voltage node in response to a load on said voltage node by others of the plurality of boost circuits in response to being selected, each of the plurality of boost circuits becoming loadless on the voltage node after said each of the plurality of boost circuits has been selected and has successively boosted said voltage on the voltage node, said each of the plurality of boost circuits becoming loadless in response to said successive boosting, all of said plurality of boost circuits being loadless on said voltage node after all of said plurality of boost circuits have been selected and have successively boosted the voltage on said voltage node; wherein the plurality of boost circuits maintain a ratio of boost capacitance to overall voltage node capacitive load for each successive boost as each of the plurality of boost circuits becomes loadless.
14. The on-chip boost circuit of claim 13 , wherein each boost circuit provides said boosting of voltage in a series of successively timed boosts.
15. The on-chip boost circuit of claim 13 , wherein each boost circuit comprises a capacitor.
16. The on-chip boost circuit of claim 15 , wherein the capacitor of a boost circuit that boosts the voltage has a capacitance such that the ratio of the capacitors of the boost circuits not previously boosting voltage maintain a predetermined ratio.
17. The on-chip boost circuit of claim 14 , wherein the successive boosting is in response to address transition detection.
18. The on-chip boost circuit of claim 17 wherein said boosting is in response to an address transition and after switching of an address decoder.
19. A charge pump system comprising: a charge pump including an oscillator and an output stage; and a plurality of boost circuits, each boost circuit coupled to the output stage, one of said plurality of boost circuits selectively and successively boosting voltage on the output stage of the charge pump and others of said plurality of boost circuits progressively boosting voltages on the progressive stages of the charge pump, each of the plurality of plurality of boost circuits increasing the boost voltage on the output stage in response to a load on said output stage by said others of said plurality of boost circuits and in response to being selected, and becoming loadless on the output stage after said each of the plurality of boost circuits successively boosted said voltage on the output stage, said each of the plurality of boost circuits becoming loadless in response to said successive boosting, all of the plurality of boost circuits being loadless on said output stage after all of the plurality of boost circuits have been selected and have successively boosted the voltage on said output stage; wherein the plurality of boost circuits maintain a ratio of boost capacitance to overall output stage capacitance for each successive boost as each of the plurality of boost circuits becomes load less.
20. The charge pump system of claim 19 wherein the boost circuits provide said boosting of voltage in a series of successively timed boosts.
21. The charge pump system of claim 19 wherein said boosting is in response to an address transition.
22. The charge pump system of claim 19 wherein said boosting is in response to an address transition and after switching of an address decoder.
23. The charge pump system of claim 19 wherein each boost circuit provides a loadless boost in voltage as a function of capacitance values of capacitors included in the boost circuits.
24. A charge pump system of claim 19 wherein each boost circuit comprises a capacitor.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 14, 2005
June 15, 2010
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