Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a first set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor structure comprising: a shallow trench isolation comprising a dielectric material and located in a semiconductor substrate; a plurality of parallel conductive lines having a width of a first sublithographic dimension and located on said semiconductor substrate, wherein each of said plurality of conductive lines has a pair of sidewall surfaces that are parallel to a first vertical plane that is orthogonal to a top surface of said semiconductor substrate, wherein each adjacent pair of said parallel conductive lines is separated by a second sublithographic dimension, and wherein multiple edges of said plurality of parallel conductive lines are located substantially on a second vertical plane that is orthogonal to said top surface of said semiconductor substrate and located at a non-orthogonal angle from said first vertical plane, each of said multiple edges being directly adjoined to one of said pairs of sidewall surfaces; a first electrode contacting all of said plurality of parallel conductive lines; and a second electrode contacting only one of said plurality of parallel conductive lines.
2. The semiconductor structure of claim 1 , wherein said plurality of parallel conductive lines comprises a semiconductor material.
3. The semiconductor structure of claim 1 , wherein said plurality of parallel conductive lines comprises a metal or a metal semiconductor alloy.
4. The semiconductor structure of claim 1 , wherein edges of said plurality of parallel conductive lines are located substantially on the same line located at a non-orthogonal angle from the direction of said parallel conductive lines.
5. The semiconductor structure of claim 1 , wherein said second electrode contacts only one of said plurality of parallel conductive lines.
6. The semiconductor structure of claim 1 , wherein the entirety of bottom surfaces of said plurality of parallel conductive lines, said first electrode, and said second electrode abut a top surface of said shallow trench isolation.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 31, 2007
June 22, 2010
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