Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such devices. Selectively controlling the temperature changes in different devices during a rapid thermal anneal is accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures. Alternatively, it is accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor structure comprising: a substrate; an insulator layer on said substrate, said insulator layer covering said substrate and having a top surface; a first film above and in contact with said top surface of said insulator layer, wherein said first film comprises a first material; and a trench isolation region comprising: a trench extending vertically through said first film to said top surface of said insulator layer and separating said first film into a first portion and a second portion; and a second film within said trench above and in contact with said top surface of said insulator layer, wherein said second film extends laterally from said first portion of said first film to said second portion of said first film, wherein said second film comprises a second material that is different from said first material, and wherein said second film comprises a first section in contact with said first portion of said first film and having a first thickness and a second section in contact with said second portion of said first film and having a second thickness that is different from said first thickness, said first thickness and said second thickness being predetermined such that said first portion of said first film exhibits first reflectance and absorption characteristics and said second portion of said first film exhibits second reflectance and absorption characteristics that are selectively different from said first reflectance and absorption characteristics.
2. The semiconductor structure of claim 1 , wherein said first thickness and said second thickness are each predetermined such that variations in reflectance and absorption characteristics between said first portion of said first film and said first section of said second film and between said second portion of said first film and said second section of said second film are selectively controlled.
3. The semiconductor structure of claim 1 , further comprising: a first device in said first portion of said first film adjacent to said first section of said second film and a second device in said second portion of said first film adjacent to said second section of said second film, wherein said first thickness of said first section of said second film and said second thickness of said second section of said second film are predetermined such that said first device and said second device achieve predetermined maximum temperatures during a single rapid thermal anneal.
4. The semiconductor structure of claim 3 , wherein said first thickness and said second thickness are further predetermined such that said first device and said second device exhibit predetermined performance characteristics following said single rapid thermal anneal.
5. The semiconductor structure of claim 1 , wherein said first material comprises a semiconductor and said second material comprises an isolation material.
6. The semiconductor structure of claim 1 , wherein said second material and said insulator layer comprise a same dielectric material.
7. A method of forming a semiconductor structure, said method comprising: providing a substrate; forming an insulator layer on said substrate such that said insulator layer covers said substrate and has a top surface, said top surface being essentially planar and continuous; forming a first film, comprising a first material, above and in contact with said insulator layer; and forming a trench isolation region in said first film, said forming of said trench isolation region comprising: forming a trench that extends vertically through said first film to said top surface of said insulator layer, separating said first film into a first portion and a second portion; forming, within said trench, a second film, comprising a second material that is different from said first material, such that said second film is above and in contact with said insulator layer, such that said second film extends laterally from said first portion of said first film to said second portion of said first film and further such that said second film comprises a first section in contact with said first portion of said first film and having a first thickness and a second section in contact with said second portion of said first film and having a second thickness that is different from said first thickness, said first thickness and said second thickness being predetermined such that said first portion of said first film exhibits first reflectance and absorption characteristics and said second portion of said first film exhibits second reflectance and absorption characteristics that are selectively different from said first reflectance and absorption characteristics.
8. The method of claim 7 , said forming, within said trench, of said second film such that said second film comprises said first section in contact with said first portion of said first film and having said first thickness and said second section in contact with said second portion of said first film and having said second thickness that is different from said first thickness comprises: depositing said second material in said trench such that said second film is formed on said insulator layer between said first portion and said second portion of said first film and such that said second film has said first thickness; depositing a photoresist layer on said first film and said second film; patterning said photoresist layer to expose said second section of said second film, leaving said first section masked; and etching back said second section of said second film such that said second section has said second thickness.
9. The method of claim 6 , wherein said method further comprises: forming a first device in said first portion of said first film adjacent to said first section of said second film and a second device in said second portion of said first film adjacent to said second section of said second film; and predetermining said first thickness of said first section and said second thickness of said second section so as to selectively control variations in reflectance and absorption characteristics between said first portion of said first film and said first section of said second film and between said second portion of said first film and said second section of said second film.
10. The method of claim 9 , further comprising predetermining said first thickness and said second thickness such that said first device and said second device achieve predetermined maximum temperatures during a single rapid thermal anneal.
11. The method of claim 9 , further comprising predetermining said first thickness and said second thickness such that said first device and said second device exhibit predetermined performance characteristics following a single rapid thermal anneal.
12. The method of claim 7 , wherein said first material comprises a semiconductor and said second material comprises an isolation material.
13. The method of claim 8 , wherein said second material and said insulator layer comprise a same dielectric material.
14. A semiconductor structure comprising: a substrate; an insulator layer above and in contact with said substrate; a semiconductor layer above and in contact with said insulator layer, said semiconductor layer comprising: a first section comprising at least one first device and a second section comprising at least one second device; a first trench isolation region extending vertically through said semiconductor layer in said first section, said first isolation region positioned laterally adjacent to said first device; a second trench isolation region extending vertically through said semiconductor layer in said second section, said second isolation region positioned laterally adjacent to said second device; and a plurality of fill structures adjacent to said first isolation region and said second isolation region, wherein a first pattern of said fill structures in said first section is such that a first amount of an isolation material in said first trench isolation region is exposed, wherein a second pattern of said fill structures in said second section is such that a second amount of said isolation material in said second trench isolation region is exposed, said first pattern being different from said second pattern and said first amount being different from said second amount, and wherein said fill structures comprise at least one of the following: single crystalline semiconductor structures within and at a top surface of at least one of said first trench isolation region and said second trench isolation region; and polycrystalline semiconductor structures above and in contact with at least a portion of at least one of said first trench isolation region and said second trench isolation region.
15. The semiconductor structure of claim 14 , wherein said single crystalline semiconductor structures comprise a silicon material and wherein said polycrystalline semiconductor structures comprise a polysilicon material.
16. The semiconductor structure of claim 14 , wherein said dielectric structures comprises one of an oxide material, a nitride material and an oxide-nitride stack.
17. The semiconductor structure of claim 14 , wherein said first amount of said isolation material exposed in said first section and said second amount of said isolation material exposed in said second section are such that said first device and said second device achieve predetermined maximum temperatures during a single rapid thermal anneal.
18. The semiconductor structure of claim 17 , wherein said predetermined maximum temperatures achieved by said first device and said second device are different dopant activation temperatures.
19. The semiconductor structure of claim 14 , wherein said first amount of said isolation material exposed in said first section and said second amount of said isolation material exposed in said second section are each such that said first device and said second device exhibit predetermined performance characteristics following a single rapid thermal anneal.
20. The semiconductor structure of claim 14 , said fill structures further comprising dielectric structures above and in contact with any one of said first isolation region, said second isolation region, a single crystalline semiconductor structure and a polycrystalline semiconductor structure.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 26, 2007
June 29, 2010
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