A semiconductor device minimizes generation of an output signal skew of an input buffer and thus stabilizes the operation of the semiconductor device. The semiconductor integrated circuit includes an input potential detection unit outputting a detection signal in response to a level of an input signal, an input buffer buffering the input signal, and an output path control unit that receives the output signal of the input buffer and the detection signal of the input potential detection unit and outputs an output driving signal in response to the level of the detection signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: an input potential detection unit receiving an input signal and outputting a detection signal in response to a level of the input signal, wherein the input potential detection unit comprises: a reference voltage generation unit generating a reference voltage; an input unit receiving the reference voltage and transmitting the reference voltage in response to the level of the input signal; and an output control unit receiving the reference voltage transmitted from the input unit and outputting the reference voltage transmitted from the input unit as the detection signal in response to an activation of an enable signal; an input buffer receiving the input signal and buffering the input signal; and an output path control unit receiving both an output signal of the input buffer and the detection signal of the input potential detection unit and outputting an output driving signal in response to a level of the detection signal.
2. The semiconductor device as set forth in claim 1 , wherein the input unit transmits the reference voltage when the level of the input signal is lower than a predetermined level.
3. The semiconductor device as set forth in claim 1 , wherein the enable signal is an enable signal' of the input buffer.
4. The semiconductor device as set forth in claim 1 , wherein the input buffer is a buffer in such a structure that differentially amplifies the input signal through a current sink unit.
5. The semiconductor device as set forth in claim 4 , wherein the input buffer is driven in response to an activation of an enable signal.
6. The semiconductor device as set forth in claim 1 , wherein the output path control unit comprises: a first path control unit receiving and combining together the output signal of the input buffer and the detection signal as an output signal of the first path control unit; a second path control unit receiving and combining together the output signal of the input buffer and the detection signal control unit and delaying and transmitting the output signal of the second path control unit; and an output unit receiving and combining together the output signal of the first path control unit and the output signal of the second path control unit and generating an output driving signal.
7. The semiconductor device as set forth in claim 6 , wherein the first path control unit comprises a first decoder receiving the output signal of the input buffer and an activated input signal of the detection signal.
8. The semiconductor device as set forth in claim 7 , wherein the first decoder comprises a NAND gate.
9. The semiconductor device as set forth in claim 7 , wherein the second path control unit comprises: a second decoder receiving the output signal of the input buffer and an inactivated signal of the detection signal; and a delay unit delaying and transmitting the output signal of the second decoder.
10. The semiconductor device as set forth in claim 9 , wherein the second decoder comprises a NAND gate.
11. The semiconductor device as set forth in claim 9 , wherein the output path control unit comprises a third decoder receiving and combining together the output signal of the first path control unit and the output signal of the second path control unit, and the third decoder generating the output driving signal.
12. The semiconductor device as set forth in claim 11 , wherein the third decoder comprises a NAND gate.
13. A semiconductor device, comprising: an input potential detection unit outputting a detection signal in response to a level of an input signal, wherein the input potential detection unit comprises: a reference voltage generation unit generating a reference voltage; an input unit receiving the reference voltage and transmitting the reference voltage in response to the level of the input signal; and an output control unit receiving the reference voltage transmitted from the input unit and outputting the reference voltage transmitted from the input signal as the detection signal in response to an activation of an enable signal; an input buffer including a buffer unit that buffers the input signal; and an output path control unit receiving both an output signal of the input buffer and the detection signal, and the output path control unit generating an output driving signal in response to the level of the detection signal and the output signal of the input buffer unit.
14. The semiconductor device as set forth in claim 13 , wherein the input unit transmits the reference voltage when the level of the input signal is lower than a predetermined level.
15. The semiconductor device as set forth in claim 13 , wherein the enable signal is an enable signal of the input buffer.
16. The semiconductor device as set forth in claim 13 , wherein the buffer unit of the input buffer is a buffer in a structure that differentially amplifies the input signal through a current sink unit.
17. The semiconductor device as set forth in claim 16 , wherein the buffer unit of the input buffer is driven in response to an activation of an enable signal.
18. The semiconductor device as set forth in claim 13 , wherein the output path control unit comprises: a first path control unit receiving and combining together the output signal of the input buffer and the detection signal as an output signal of the first path control unit; a second path control unit receiving and combining together the output signal of the input buffer and the detection signal as an output signal of the second path control unit, and delaying and transmitting the output signal of the second path control unit; and an output unit receiving the output signal of the first path control unit and the output signal of the second path control unit and generating the output driving signal.
19. The semiconductor device as set forth in claim 18 , wherein the first path control unit comprises a first decoder receiving the output signal of the input buffer and an activated input signal of the detection signal.
20. The semiconductor device as set forth in claim 19 , wherein the second path control unit comprises: a second decoder receiving the output signal of the input buffer and an inactivated signal of the detection signal; and a delay unit delaying and transmitting the output signal of the second decoder.
21. The semiconductor device as set forth in claim 18 , wherein the output unit further comprises a third decoder receiving and combining together the output signal of the first path control unit and the output signal of the second path control unit, and the third decoder generating the output driving signal.
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June 11, 2008
July 6, 2010
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