A semiconductor memory device includes a memory cell group, a selection transistor, a page buffer, and a row decoder. The memory cell group includes memory cell transistors connected in series. The selection transistor is connected to the memory cell transistor. The page buffer is adopted to apply first and second voltages to the bit lines connected to the memory cell transistors in which the “0” data and “1” data is to be programmed respectively, when the selection transistor is turned on, in a write operation. The page buffer is adopted to put the bit line into electrically floating after the first voltage and the second voltage are applied. The row decoder is adopted to apply a third voltage to a semiconductor layer on which the memory cell transistors are formed, and apply a program voltage to the selected word line when the bit line is in the electrically floating.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device comprising: memory cell transistors which are formed on a semiconductor layer, each of the memory cell transistors having a stacked gate including a charge accumulation layer and a control gate, the memory cell transistors being capable of retaining “0” data or “1” data based on whether or not a charge is injected into the charge accumulation layer; a memory cell group in which current passages of the memory cell transistors are connected in series; a selection transistor which has a current passage connected in series to one of the memory cell transistors located closest to a drain side in the memory cell group; a memory cell array in which the memory cell group and the selection transistor are arranged; a bit line which is connected to a drain of the memory cell transistor through the current passage of the selection transistor; a page buffer which is adopted to apply a first voltage to the bit line connected to the memory cell transistor in which the “0” data is to be programmed and apply a second voltage larger than the first voltage to the bit line connected to the memory cell transistor in which the “1” data is to be programmed, when the selection transistor is turned on, in a write operation of the data, the page buffer being adopted to put the bit line into electrically floating state after the first voltage and the second voltage are applied; a word line which is connected to the control gate of the memory cell transistor; and a row decoder which is adopted to apply a positive third voltage to the semiconductor layer, select the word line connected to the memory cell transistor to be programmed, and apply a program voltage to the selected word line when the bit line is in the electrically floating state.
2. The device according to claim 1 , wherein the row decoder cuts off the memory cell transistor located closer to a source side than the memory cell transistor in which the data is programmed before the program voltage is applied.
3. The device according to claim 1 , wherein the page buffer selects the bit lines in the write operation, the data is collectively written to the memory cell transistors connected to the selected bit lines, and the page buffer applies a fourth voltage to an unselected bit line while applying the first voltage and the second voltage to the selected bit line in the write operation of the data.
4. The device according to claim 3 , wherein the page buffer puts the selected bit line into the electrically floating state, and the page buffer applies a fifth voltage larger than the fourth voltage to the unselected bit line.
5. The device according to claim 4 , wherein a potential at the selected bit line is increased by coupling to the semiconductor layer and the unselected bit line.
6. The device according to claim 1 , wherein when the program voltage is applied to the word line, the row decoder turns on the selection transistor connected to the bit line to which the first voltage is applied and turns off the selection transistor connected to the bit line to which the second voltage is applied, and the row decoder applies the fourth voltage smaller than the program voltage to an unselected word line to turn on the memory cell transistor connected to the unselected word line.
7. The device according to claim 6 , wherein the row decoder applies the fourth voltage to an unselected word line located on the drain side after applying the fourth voltage to the unselected word line located closer to a source side than the selected word line.
8. The device according to claim 1 , wherein before the program voltage is applied, the row decoder turns on all the memory cell transistors in the memory cell group including the memory cell transistor to be programmed by applying a fourth voltage to all the word lines.
9. A data write method of a NAND flash memory comprising: applying a first voltage to a first bit line connected to a memory cell transistor in which “0” data is to be programmed when a selection transistor is turned on; applying a second voltage larger than the first voltage to a second bit line connected to a memory cell transistor in which “1” data is to be programmed when the selection transistor is turned on; putting the first bit line and the second bit line into electrically floating state after the first voltage and the second voltage are applied; increasing a potential at a semiconductor layer by applying a third voltage to the semiconductor layer on which the memory cell transistor is formed after the first voltage and the second voltage are applied; and programming data to the memory cell transistor by selecting a word line and applying a program voltage to the selected word line in a state that potentials at the first bit line and the second bit line are put into floating and a potential at the semiconductor layer is increased.
10. The method according to claim 9 , wherein a memory cell transistor located closer to a source side than the memory cell transistor connected to the selected word line is cut off when the data is programmed.
11. The method according to claim 9 , further comprising applying a fourth voltage to a third bit line which is not connected to the memory cell transistor to be programmed, when the selection transistor is turned on.
12. The method according to claim 11 , further comprising applying a fifth voltage larger than the fourth voltage to the third bit line after the first, second, and fourth voltages are applied.
13. The method according to claim 12 , wherein a potential at the selected bit line is increased by coupling to the semiconductor layer and the unselected bit line.
14. The method according to claim 9 , further comprising: turning on the selection transistor connected to the first bit line and turning off the selection transistor connected to the second bit line; and applying a fourth voltage smaller than the program voltage to an unselected word line to turn on the memory cell transistor connected to the unselected word line, wherein the data is programmed in a state that the selection transistors connected to the first and second bit lines are respectively turned on and off and the fourth voltage is applied to the unselected word line.
15. The method according to claim 9 , further comprising turning on all the memory cell transistors in the memory cell group including the memory cell transistor to be programmed by applying a fourth voltage to all the word lines after the first and second bit lines are put into floating state.
16. The method according to claim 14 , wherein, the fourth voltage is applied to an unselected word line located closer to a drain side than the selected word line after applying to an unselected word line located closer to a source side than the selected word line.
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September 11, 2008
July 6, 2010
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