A device, system and method adapted to expand a high speed data bus, such as a PCI Express (PCIe) bus, over a serial link with an expansion unit having a high speed data bus, such as a PCIe bus, without using a bridging or switching device. One primary advantage of not using a bridge or switch is that the expansion interface is completely transparent to the BIOS, processor, CPU, OS, or any other component(s) on the host motherboard be they hardware, firmware, or software. This invention does not require additional protocols such as TCP/IP, Serial ATA, Gigabit Ethernet, etc. There is also no implicit hardware or device driver latency resulting from a bridge or switch.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A PCI Express (PCIe) communication system comprising: a host receiving bus data and power, configured to serially transmit PCIe compliant signals; a serial link electrically coupled to the host; a receiver electrically coupled to the serial link and configured to receive the serially transmitted PCIe signals; a driver electrically coupled to the host and configured to amplify the transmitted PCIe signals, whereby the amplified PCIe signals sent by the driver do not meet the PCIe Specification requirements, but which said amplified PCIe signals do meet the PCIe Specification requirements at the receiver; and the host including an interface processing a sideband signal such that the side band signal is passed after the power has stabilized.
2. The PCIe communication system as specified in claim 1 wherein the serial link can be, but is not required to be, a PCIe Specification compliant cable.
3. The PCIe communication system as specified in claim 1 wherein the interface is synchronized with the host power and is adapted to process a PERST# sideband signal.
4. The PCIe communication system as specified in claim 3 wherein the interface delays the PERST# signal until the power is stable a predetermined time period.
5. A driver adapted to couple to a data bus having power and amplify received PCIe compliant signals, whereby the PCIe compliant signals sent by the driver do not meet the PCIe Specification requirements, which said received signals do meet the PCIe Specification requirements without the driver, and further including an interface processing a sideband signal such that the sideband signal is sent after the power has stabilized.
6. The driver as specified in claim 5 wherein the driver is configured to deliver the PCIe signals that meet the PCIe Specification at a receiver when sent over the cable which cable may not be compliant with the PCIe Specification.
7. PCI Express (PCIe) communication system comprising: a host receiving bus data and power, configured to serially transmit PCIe compliant signals; a serial link electrically coupled to the host; a receiver electrically coupled to the serial link and configured to receive the serially transmitted PCIe signals; a driver electrically coupled to the host and configured to amplify the transmitted PCIe signals, whereby the amplified PCIe signals sent by the driver do not meet the PCIe Specification requirements, but which said amplified PCIe signals do meet the PCIe Specification requirements at the receiver; and processing means for processing a sideband signal such that the side band signal is passed after the power has stabilized.
8. The PCIe communication system as specified in claim 7 wherein the serial link can be, but is not required to be, a PCIe Specification compliant cable.
9. The PCIe communication system as specified in claim 7 wherein the processing means is synchronized with the host power and is adapted to process a PERST# sideband signal.
10. The PCIe communication system as specified in claim 9 wherein the processing means delays the PERST# signal until the power is stable a predetermined time period.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 20, 2006
July 6, 2010
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