Method for making a coreless packaging substrate are disclosed in the present invention. The coreless packaging substrate is made by first providing a metal adhesion layer having a melting point lower than that of the substrate, and removing a core board connected with the substrate therefrom through melting the metal adhesion layer. In addition, the disclosed packaging substrate further includes a circuit built-up structure of which has the electrical pads embedded under a surface. The disclosed packaging substrate can achieve the purposes of reducing the thickness, increasing circuit layout density, and facilitating the manufacturing of the substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for manufacturing a coreless packaging substrate comprising the following steps: providing a core board; forming a metal adhesive layer on the surface of the core board; forming a patterned first solder mask layer on the surface of the metal adhesive layer, wherein the first solder mask layer has a plurality of first openings; forming a metal pillar in each of the first openings, and forming a metal layer on the surface of the metal pillar and part of the surface of the first solder mask layer; forming a circuit built-up structure on the surfaces of the metal layer and the first solder mask layer, wherein the metal layer is embedded in the circuit built-up structure; forming a patterned second solder mask layer on the circuit built-up structure, wherein the second solder mask layer has a plurality of second openings exposing circuits of the circuit built-up structure, and the exposed circuits serve as second conductive pads; and removing the core board and the metal adhesive layer to expose the metal pillar serving as first conductive pads.
2. The method as claimed in claim 1 , wherein the first conductive pads are bump pads electrically connected to a chip, and the second conductive pads are ball pads electrically connected to an electronic device.
3. The method as claimed in claim 1 , wherein the first conductive pads are ball pads electrically connected to an electronic device, and the second conductive pads are bump pads electrically connected to a chip.
4. The method as claimed in claim 1 , wherein the metal adhesive layer is formed by electroplating or electroless plating.
5. The method as claimed in claim 1 , wherein the metal adhesive layer is made of a metal having a melting point lower than that of the packaging substrate.
6. The method as claimed in claim 5 , wherein the metal is Sn.
7. The method as claimed in claim 1 , wherein the core board is a copper clad laminate.
8. The method as claimed in claim 1 , further comprising a step of forming a seed layer prior to formation of the metal pillar and the metal layer.
9. The method as claimed in claim 1 , wherein the respective metal pillar and the metal layer are formed at the same time.
10. The method as claimed in claim 1 , wherein the metal pillar and the metal layer are made of Cu.
11. The method as claimed in claim 1 , wherein the first and second openings are formed by photolithography.
12. The method as claimed in claim 1 , wherein the circuit built-up structure comprises a dielectric layer, circuit layers disposed on the dielectric layer, and conductive vias formed in the dielectric layer.
13. The method as claimed in claim 1 , wherein the circuit built-up structure is single-layered or multilayer.
14. The method as claimed in claim 1 , wherein the core board and the metal adhesive layer are removed by thermomelting.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 5, 2008
July 13, 2010
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.