Voltage generating circuit and semiconductor memory device with the same

1. A voltage generating circuit comprising: a pumping circuit configured to boost a power supply voltage in accordance with a charge transfer operation; a voltage detection circuit configured to detect the output voltage of the pumping circuit; a first pumping control circuit configured to control the pumping circuit in accordance with the output of the voltage detection circuit; and a second pumping control circuit configured to control the pumping circuit in place of the first pumping control circuit when the output voltage of the pumping circuit is in a certain range; wherein the pumping circuit comprises, a charge transfer circuit having multiple diodes connected in series between a power supply node and the voltage output node of the pumping circuit and capacitors, one ends thereof being coupled to the respective connection nodes of the diodes, for boosting the power supply voltage in accordance with one directional charge transferring, a first clock generating circuit selected by the first pumping control circuit to drive the other ends of the capacitors of the charge transfer circuit with a constant clock frequency, and a second clock generating circuit selected by the second pumping control circuit to drive the other ends of the capacitors of the charge transfer circuit with a variable clock frequency.

2. The voltage generating circuit according to claim 1 , further comprising: a ROM circuit configured to store the control data of the second pumping control circuit, the control data being determined based on the previously measured leakage property of the pumping circuit and written in the ROM circuit.

3. The voltage generating circuit according to claim 1 , further comprising: a switching circuit configured to select one of the control signals of the first and second pumping control circuits and transfer it to the pumping circuit.

4. The voltage generating circuit according to claim 3 , wherein the voltage detection circuit comprises: a resistance divider circuit having multiple resistances connected in series between the voltage output node of the pumping circuit and the ground potential node; a first comparator for comparing the voltage at a first tap of the resistance divider circuit with a reference voltage to detect that the output voltage of the pumping circuit reaches a first level; and a second comparator for comparing the voltage at a second tap of the resistance divider circuit with the reference voltage to detect that the output voltage of the pumping circuit reaches a second level higher than the first level, and wherein the switching circuit is controlled by the first and second comparators to transfer the control signal of the second pumping control circuit to the pumping circuit in place of the first pumping control circuit when the output voltage of the pumping circuit is between the first level and the second level.

5. The voltage generating circuit according to claim 1 , further comprising: a switching control circuit configured to activate one of the first and second pumping control circuits and set the other in an inactive state with high output impedance.

6. The voltage generating circuit according to claim 5 , wherein the voltage detection circuit comprises: a resistance divider circuit having multiple resistances connected in series between the voltage output node of the pumping circuit and the ground potential node; a first comparator for comparing the voltage at a first tap of the resistance divider circuit with a reference voltage to detect that the output voltage of the pumping circuit reaches a first level; and a second comparator for comparing the voltage at a second tap of the resistance divider circuit with the reference voltage to detect that the output voltage of the pumping circuit reaches a second level higher than the first level, and wherein the switching control circuit activates the second pumping control circuit in place of the first pumping control circuit when the output voltage of the pumping circuit is between the first level and the second level in accordance with the output state of the first and second comparators.

7. The voltage generating circuit according to claim 1 , wherein the pumping circuit has n(≧2) pumps disposed in parallel, which are driven by the respective clocks with phase difference of 2π/n from each other.

8. A semiconductor memory device with an internal voltage generating circuit, the internal voltage generating circuit comprising: a pumping circuit configured to boost a power supply voltage in accordance with a charge transfer operation; a voltage detection circuit configured to detect the output voltage of the pumping circuit; a first pumping control circuit configured to control the pumping circuit in accordance with the output of the voltage detection circuit; and a second pumping control circuit configured to control the pumping circuit in place of the first pumping control circuit when the output voltage of the pumping circuit is in a certain range; wherein the pumping circuit comprises, a charge transfer circuit having multiple diodes connected in series between a power supply node and the voltage output node of the pumping circuit and capacitors, one ends thereof being coupled to the respective connection nodes of the diodes, for boosting the power supply voltage in accordance with one directional charge transferring, a first clock generating circuit selected by the first pumping control circuit to drive the other ends of the capacitors of the charge transfer circuit with a constant clock frequency, and a second clock generating circuit selected by the second pumping control circuit to drive the other ends of the capacitors of the charge transfer circuit with a variable clock frequency.

9. The semiconductor memory device according to claim 8 , wherein the internal voltage generating circuit further comprises: a ROM circuit configured to store the control data of the second pumping control circuit, the control data being determined based on the previously measured leakage property of the pumping circuit and written in the ROM circuit.

10. The semiconductor memory device according to claim 1 , wherein the internal voltage generating circuit further comprises: a switching circuit configured to select one of the control signals of the first and second pumping control and transfer it to the pumping circuit.

11. The semiconductor memory device according to claim 10 , wherein the voltage detection circuit comprises: a resistance divider circuit having multiple resistances connected in series between the voltage output node of the pumping circuit and the ground potential node; a first comparator for comparing the voltage at a first tap of the resistance divider circuit with a reference voltage to detect that the output voltage of the pumping circuit reaches a first level; and a second comparator for comparing the voltage at a second tap of the resistance divider circuit with the reference voltage to detect that the output voltage of the pumping circuit reaches a second level higher than the first level, and wherein the switching circuit is controlled by the first and second comparators to transfer the control signal of the second pumping control circuit to the pumping circuit in place of the first pumping control circuit when the output voltage of the pumping circuit is between the first level and the second level.

12. The semiconductor memory device according to claim 8 , wherein the internal voltage generating circuit further comprises: a switching control circuit configured to activate one of the first and second pumping control circuits and set the other in an inactive state with high output impedance.

13. The semiconductor memory device according to claim 12 , wherein the voltage detection circuit comprises: a resistance divider circuit having multiple resistances connected in series between the voltage output node of the pumping circuit and the ground potential node; a first comparator for comparing the voltage at a first tap of the resistance divider circuit with a reference voltage to detect that the output voltage of the pumping circuit reaches a first level; and a second comparator for comparing the voltage at a second tap of the resistance divider circuit with the reference voltage to detect that the output voltage of the pumping circuit reaches a second level higher than the first level, and wherein the switching control circuit activates the second pumping control circuit in place of the first pumping control circuit when the output voltage of the pumping circuit is between the first level and the second level in accordance with the output state of the first and second comparators.

14. The semiconductor memory device according to claim 8 , wherein the pumping circuit has n(≧2) pumps disposed in parallel, which are driven by the respective clocks with phase difference of 2π/n from each other.

15. The semiconductor memory device according to claim 8 , wherein the memory device has a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged.

16. The semiconductor memory device according to claim 15 , wherein the memory cell array has NAND cell units arranged therein, each of which has multiple memory cells corrected in series.

17. The semiconductor memory device according to claim 15 , wherein the memory device stores data of multi bits per cell.