In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A nonvolatile semiconductor memory device comprising a plurality of memory units arranged in array and each including a read device, an erase device, and a decode device, each of which is composed of a MOS transistor, wherein in each of the memory units, the read device and the erase device are connected to each other, the read device and the erase device share a gate, and an output side of the decode device, which is controlled by a row selection signal and a column selection signal, is connected to the erase device.
2. The nonvolatile semiconductor memory device of claim 1 , wherein the column selection signal of the decode device is generated from a program signal and a data signal.
3. The nonvolatile semiconductor memory device of claim 1 , wherein the column selection signal of the decode device is generated from an address signal, a data signal and a program signal.
4. The nonvolatile semiconductor memory device of claim 1 , wherein the decode device is composed of a NAND circuit.
5. The nonvolatile semiconductor memory device of claim 1 , wherein a part under a drain of at least one MOS transistor of the decode device is subjected to well injection.
6. The nonvolatile semiconductor memory device of claim 1 , further comprising: a capacitance coupling device connected to the gate shared by read device and the erase device in each of the memory units.
7. The nonvolatile semiconductor memory device of claim 1 , wherein a thickness of a gate oxide film of each MOS transistor composing the respective memory units is substantially equal to a thickness of a gate oxide film of a MOS transistor forming an input/output circuit of an LSI.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 9, 2008
July 13, 2010
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.