The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A verify method of a semiconductor device including a NAND cell having a first and second nonvolatile memory elements connected in series, comprising: setting potential of a control gate of the first nonvolatile memory element to be a first potential and potential of a control gate of the second nonvolatile memory element to be a second potential, for erasing a data stored in the first nonvolatile memory element; and setting potential of a control gate of the first nonvolatile memory element to be a third potential and potential of a control gate of the second nonvolatile memory element to be the second potential, for reading a data stored in the first nonvolatile memory element after erasing a data stored in the first nonvolatile memory element, wherein each of the first and second nonvolatile memo elements has a semiconductor layer including a channel forming region and a floating gate, and wherein the floating gate is formed from a semiconductor material having a smaller energy gap than the semiconductor layer.
2. The verify method according to claim 1 , wherein each of the first and second nonvolatile memory elements has a semiconductor layer including a channel forming region and a floating gate, and wherein the floating gate is formed from germanium or a germanium compound.
3. The verify method according to claim 1 , wherein the semiconductor device is incorporated in at least one of electronic devices selected from the group consisting of a camera, a goggle display, a navigation system, an audio reproducing apparatus, a computer, a game machine, a portable information terminal, and an image reproducing device.
4. The verify method according to claim 1 , wherein the semiconductor device is incorporated in at least one of paper money, a coin, securities, a certificate, a bearer bond, a packaging container, a book, a recording media, a vehicle, a food, a clothing, a health product, a commodity, and chemicals.
5. The verify method according to claim 1 , wherein the first and second nonvolatile memory elements share a same semiconductor layer.
6. The verify method according to claim 1 , wherein the first and second nonvolatile memory elements are formed over a substrate containing silicon.
7. A verify method of a semiconductor device including a NAND cell having a plurality of nonvolatile memory elements connected in series, comprising: selecting one of the plurality of nonvolatile memory elements; setting potential of control gates of the plurality of nonvolatile memory elements so that potential of the selected nonvolatile memory element to be a first potential and the other nonvolatile memory elements to be a second potential, while erasing a data stored in the selected nonvolatile memory element; and setting potential of control gates of the plurality of nonvolatile memory elements so that potential of the selected nonvolatile memory element to be a third potential and the other nonvolatile memory elements to be the second potential, while reading a data stored in the selected nonvolatile memory element after erasing a data stored in the selected nonvolatile memory element, wherein each of the plurality of nonvolatile memo elements has a semiconductor layer including a channel forming region and a floating gate, and wherein the floating gate is formed from a semiconductor material having a smaller energy gap than the semiconductor layer.
8. The verify method according to claim 7 , wherein each of the plurality of nonvolatile memory elements has a semiconductor layer including a channel forming region and a floating gate, and wherein the floating gate is formed from germanium or a germanium compound.
9. The verify method according to claim 7 , wherein the semiconductor device is incorporated in at least one of electronic devices selected from the group consisting of a camera, a goggle display, a navigation system, an audio reproducing apparatus, a computer, a game machine, a portable information terminal, and an image reproducing device.
10. The verify method according to claim 7 , wherein the semiconductor device is incorporated in at least one of paper money, a coin, securities, a certificate, a bearer bond, a packaging container, a book, a recording media, a vehicle, a food, a clothing, a health product, a commodity, and chemicals.
11. The verify method according to claim 7 , wherein the plurality of nonvolatile memory elements share a same semiconductor layer.
12. The verify method according to claim 7 , wherein the plurality of nonvolatile memory elements are formed over a substrate containing silicon.
13. A verify method of a semiconductor device including a NAND cell having a first and second nonvolatile memory elements connected in series over a substrate having an insulating surface, comprising: setting potential of a control gate of the first nonvolatile memory element to be a first potential and potential of a control gate of the second nonvolatile memory element to be a second potential, for erasing a data stored in the first nonvolatile memory element; and setting potential of a control gate of the first nonvolatile memory element to be a third potential and potential of a control gate of the second nonvolatile memory element to be the second potential, for reading a data stored in the first nonvolatile memory element after erasing a data stored in the first nonvolatile memory element, wherein each of the first and second nonvolatile memo elements has a semiconductor layer including a channel forming region and a floating gate, and wherein the floating gate is formed from a semiconductor material having a smaller energy gap than the semiconductor layer.
14. The verify method according to claim 13 , wherein each of the first and second nonvolatile memory elements has a semiconductor layer including a channel forming region and a floating gate, and wherein the floating gate is formed from germanium or a germanium compound.
15. The verify method according to claim 13 , wherein the semiconductor device is incorporated in at least one of electronic devices selected from the group consisting of a camera, a goggle display, a navigation system, an audio reproducing apparatus, a computer, a game machine, a portable information terminal, and an image reproducing device.
16. The verify method according to claim 13 , wherein the semiconductor device is incorporated in at least one of paper money, a coin, securities, a certificate, a bearer bond, a packaging container, a book, a recording media, a vehicle, a food, a clothing, a health product, a commodity, and chemicals.
17. The verify method according to claim 13 , wherein the first and second nonvolatile memory elements share a same semiconductor layer.
18. The verify method according to claim 13 , wherein the first and second nonvolatile memory elements are formed over a substrate containing silicon.
19. The verify method according to claim 13 , wherein the substrate having an insulating surface is a glass substrate.
20. A verify method of a semiconductor device including a NAND cell having a plurality of nonvolatile memory elements connected in series over a substrate having an insulating surface, comprising: selecting one of the plurality of nonvolatile memory elements; setting potential of control gates of the plurality of nonvolatile memory elements so that potential of the selected nonvolatile memory element to be a first potential and the other nonvolatile memory elements to be a second potential, while erasing a data stored in the selected nonvolatile memory element; and setting potential of control gates of the plurality of nonvolatile memory elements so that potential of the selected nonvolatile memory element to be a third potential and the other nonvolatile memory elements to be the second potential, while reading a data stored in the selected nonvolatile memory element after erasing a data stored in the selected nonvolatile memory element, wherein each of the plurality of nonvolatile memory elements has a semiconductor layer including a channel forming region and a floating gate, and wherein the floating gate is formed from a semiconductor material having a smaller energy gap than the semiconductor layer.
21. The verity method according to claim 20 , wherein each of the plurality of nonvolatile memory elements has a semiconductor layer including a channel forming region and a floating gate, and wherein the floating gate is formed from germanium or a germanium compound.
22. The verify method according to claim 20 , wherein the semiconductor device is incorporated in at least one of electronic devices selected from the group consisting of a camera, a goggle display, a navigation system, an audio reproducing apparatus, a computer, a game machine, a portable information terminal, and an image reproducing device.
23. The verify method according to claim 20 , wherein the semiconductor device is incorporated in at least one of paper money, a coin, securities, a certificate, a bearer bond, a packaging container, a book, a recording media, a vehicle, a food, a clothing, a health product, a commodity, and chemicals.
24. The verify method according to claim 20 , wherein the plurality of nonvolatile memory elements share a same semiconductor layer.
25. The verify method according to claim 20 , wherein the plurality of nonvolatile memory elements are formed over a substrate containing silicon.
26. The verify method according to claim 20 , wherein the substrate having an insulating surface is a glass substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 28, 2007
July 20, 2010
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