Provided are a semiconductor device and a manufacturing method thereof. A pair of adjacent gate structure can be formed on a substrate. Mask patterns exposing a portion located between the gate structures are formed. The substrate portion located between the gate structures can be etched using the mask patterns as an etch mask to form a pocket. First conduction type impurities can be implanted into the pocket to form a first impurity layer in a surface of the pocket. Second conduction type impurities can be implanted into the pocket to form a second impurity layer on the first impurity layer. The pocket can be filled with an insulating material. Accordingly, impurities having a type opposite to the type of source junction impurities are implanted into the pocket to reduce a potential barrier of a source junction. Consequently, punch-through generated between a source and a drain can be inhibited.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for manufacturing a semiconductor device, the method comprising: forming a pair of adjacent gate structures on a substrate; forming mask patterns exposing a portion of the substrate located between the gate structures; etching the portion of the substrate located between the gate structures using the mask patterns as an etch mask to form a pocket; implanting first conduction type impurities into the pocket to form a first conduction type impurity layer in a surface of the pocket; implanting second conduction type impurities into the pocket to form a second conduction type impurity layer on the first conduction type impurity layer; and filling the pocket with an insulating material.
2. The method according to claim 1 , wherein the first conduction type impurities are p type impurities, and the second conduction type impurities are n type impurities.
3. The method according to claim 2 , wherein the first conduction type impurities comprise BF + ions.
4. The method according to claim 2 , wherein the second conduction type impurities comprise As + ions.
5. The method according to claim 1 , wherein the first conduction type impurities are implanted into the pocket in a direction perpendicular to the substrate, and the second conduction type impurities are implanted into the pocket in a direction inclined with respect to the substrate.
6. The method according to claim 1 , wherein the first conduction type impurities are implanted in a range of 4×10 15 -6×10 16 atoms/cm 2 , at an ion implanting energy in a range of 40-60 KeV, and the second conduction type impurities are implanted in a range of 1×10 15 -3×10 15 atoms/cm 2 at an ion implanting energy in a range of 10-30 KeV.
7. The method according to claim 1 , further comprising, after forming the first conduction type impurity layer, performing an annealing process to recover a damage of the substrate and thermally diffuse the first conduction type impurities.
8. The method according to claim 1 , wherein forming the pair of the adjacent gate structures comprises: forming a tunnel oxide layer on the substrate, a floating gate layer on the tunnel oxide layer, an ONO layer on the floating gate layer, and a control gate layer on the ONO layer; forming a photoresist pattern on the control gate layer; sequentially etching the tunnel oxide layer, the floating gate layer, the ONO layer, and the control gate layer using the photoresist pattern as an etch mask to form the gate structures including a tunnel oxide layer pattern, a floating gate, an ONO pattern, and a control gate.
9. The method according to claim 8 , wherein the mask pattern exposes at least portions of upper surfaces of the gate structures.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 29, 2007
July 27, 2010
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