A device package that receives a voltage from a power supply on a motherboard and that includes provisions for a voltage control element that controls the power supply voltage. The provisions for the voltage control element are such that the voltage from the power supply has a first voltage if the voltage control element is installed and a second voltage if the voltage control element is missing. Such a device is useful in (computer) systems having wiring boards with power supplies that produce output voltages that depend on adjust voltages on adjust inputs. The provisions of the device package can then set the adjust voltage such that the power supply has a first voltage if the voltage control element is installed and a second voltage if the voltage control element is missing.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of assembling a system comprising the steps of: coupling a memory device to a mobile application package (MAP) substrate; coupling the MAP substrate to a power supply through a first voltage control element that provides a first non-zero voltage to the memory device when operating in a first configuration and a second non-zero voltage to the memory device when operating in a second configuration.
2. The method of claim 1 further comprising coupling the MAP substrate to a circuit board such that the first voltage control element coupled to the MAP substrate is operatively connected to the circuit board.
3. The method of claim 1 wherein the first voltage control element is a first resistance element.
4. The method of claim 3 wherein the first resistance element is a low resistance element.
5. The method of claim 3 wherein the first resistance element is a voltage adjust resistor.
6. The method of claim 3 wherein the first resistance element is a conductive ball.
7. The method of claim 3 wherein the first resistance element is a fuse-able interconnect.
8. The method of claim 1 , further comprising the steps of: coupling a graphics processor to the MAP substrate; and coupling the MAP substrate to the power supply through a second voltage control element that provides a third non-zero voltage to the graphics processor when operating in a third configuration and a fourth non-zero voltage to the graphics processor when operating in a fourth configuration.
9. The method of claim 8 wherein the second voltage control element is a second resistance element.
10. The method of claim 9 wherein the second resistance element is a ball.
11. The method of claim 9 wherein the second resistance element is a fuse-able interconnect.
12. The method of claim 1 , wherein the first voltage control element is included within the MAP.
13. The method of claim 8 , wherein the second voltage control element is included within the MAP.
14. The method of claim 8 , wherein the first voltage control element operates in either the first configuration or the second configuration in conjunction with the second voltage control element operating in either the third configuration or the fourth configuration.
15. The method of claim 9 , wherein the second resistance element is a voltage adjust resistor.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 2, 2007
August 3, 2010
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