A semiconductor memory device includes a memory cell block. The memory cell block includes a plurality of n-type first MIS transistors with current passages connected in series. Each of the first MIS transistors includes a source, a drain, and a charge storage layer formed on a (001)-plane of a semiconductor substrate with a gate insulating film interposed therebetween and is configured to store data. A direction from the source to the drain in each of the first MIS transistors is set parallel to a [001]-direction or [010]-direction of the semiconductor substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device comprising: a memory cell block including a plurality of n-type first MIS transistors with current passages connected in series, each of the first MIS transistors including a source, a drain, and a charge storage layer formed on a (001)-plane of a semiconductor substrate with a gate insulating film interposed therebetween and configured to store data, and a direction from the source to the drain in each of the first MIS transistors being set parallel to a [100]-direction or [010]-direction of the semiconductor substrate.
2. The device according to claim 1 , wherein, in writing the data at each of the first MIS transistors, the source and the drain thereof are set to have an equal electric potential, while a gate thereof is supplied with a positive voltage, such that electrons are injected through the gate insulating film into the charge storage layer thereof.
3. The device according to claim 1 , wherein writing the data at each of the first MIS transistors is performed by FN tunneling.
4. The device according to claim 1 , further comprising: a selection transistor with a current passage connected in series to one of the current passages of the first MIS transistors; and a data transfer line connected to the selection transistor and configured to supply write data to the first MIS transistors through the selection transistor, wherein, in writing the data at each of the first MIS transistors, a gate voltage thereof is set to be higher than a gate voltage of the selection transistor.
5. The device according to claim 1 , further comprising: a p-type second MIS transistor formed on the (001)-plane of the semiconductor substrate, wherein a direction from a source to a drain in the second MIS transistor is set parallel to the [100]-direction or [010]-direction of the semiconductor substrate.
6. A semiconductor memory device comprising: an n-type first selection transistor formed on a (001)-plane of a semiconductor substrate; an n-type second selection transistor formed on the (001)-plane of the semiconductor substrate; and a plurality of n-type memory cell transistors with current passages connected in series between a source of the first selection transistor and a drain of the second selection transistor, each of the memory cell transistors including a charge storage layer formed on the (001)-plane of the semiconductor substrate and configured to store data, and each of the current passages of the memory cell transistors being set parallel to a [100]-direction or [010]-direction of the semiconductor substrate.
7. The device according to claim 6 , wherein the first selection transistor and the second selection transistor have current passages set parallel to the [100]-direction or [010]-direction of the semiconductor substrate.
8. The device according to claim 6 , further comprising: a control circuit configured to control at least one of a writing operation, a reading operation, and a erasing operation of data relative to the memory cell transistors, wherein the control circuit includes an n-type first MIS transistor and a p-type second MIS transistor formed on the (001)-plane of the semiconductor substrate, and the second MIS transistor has an current passage set parallel to the [100]-direction or [010]-direction of the semiconductor substrate.
9. The device according to claim 6 , wherein each of the memory cell transistors includes the charge storage layer formed on the semiconductor substrate with a gate insulating film interposed therebetween, and a control gate formed on the charge storage layer with the inter-gate insulating film interposed therebetween, and wherein, in data writing at each of the memory cell transistors, a source and a drain thereof are set to have an equal electric potential, while the control gate thereof is supplied with a positive voltage, such that electrons are injected through the gate insulating film into the charge storage layer thereof.
10. The device according to claim 6 , wherein writing the data at each of the memory cell transistors is performed by FN tunneling.
11. The device according to claim 6 , further comprising a bit line connected to a drain of the first selection transistor and configured to supply write data to the memory cell transistors through an current passage of the first selection transistor.
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June 28, 2007
August 10, 2010
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