A semiconductor memory device having a first memory cell array block including a memory cell having a floating body, the memory cell coupled to a word line, a first bit line, and a first source line, a second memory cell array block including a reference memory cell having a floating body, the reference memory cell coupled to a reference word line, a second bit line, and a second source line, a first isolation gate portion configured to selectively transmit a signal between the first bit line and at least one of a sense bit line and an inverted sense bit line, a second isolation gate portion configured to selectively transmit a signal between the second bit line and at least one of the sense bit lines, and a sense amplifier configured to amplify voltages of the sense bit line and the inverted sense bit line to first and second sense amplifying voltage levels.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device comprising: a memory cell array including a first memory cell array block and a second memory cell array block, the first memory cell array block including a memory cell having a floating body connected to a word line, a first bit line, and a first source line, the second memory cell array block including a reference memory cell having a floating body connected to a reference word line, a second bit line, and a second source line; a first isolation gate portion for transmitting a signal between the first bit line and an inverted sense bit line during a write operation and during a third period of a read operation, and for transmitting a signal between the first bit line and a sense bit line during a first period of the read operation; a second isolation gate portion for transmitting a signal between the second bit line and the inverted sense bit line during the first period of the read operation; a precharge portion for precharging the sense bit line and the inverted sense bit line to a precharge voltage level during a precharge operation; and a sense amplifier for amplifying voltages of the sense bit line and the inverted sense bit line to first and second sense amplifying voltage levels during the write operation and during a second and the third periods of the read operation.
2. The device according to claim 1 , further comprising a column selection gate portion for transmitting data between the sense bit line and a data input/output line, and for transmitting data between the inverted sense bit line and an inverted data input/output line.
3. The device according to claim 1 , wherein the sense amplifier comprises: a PMOS sense amplifier including a first PMOS transistor and a second PMOS transistor that are connected in series between the sense bit line and the inverted sense bit line and that sense high-level data of one of the sense bit line and the inverted sense bit line to amplify the high-level data to the first sense amplifying voltage level; and an NMOS sense amplifier including a first NMOS transistor and a second NMOS transistor that are connected in series between the sense bit line and the inverted sense bit line and that sense low-level data of one of the sense bit line and the inverted sense bit line to amplify the low-level data to the second sense amplifying voltage level.
4. The device according to claim 3 , wherein the reference memory cell has a threshold voltage that is higher than a threshold voltage of the memory cell when the memory cell stores data “1” and lower than a threshold voltage of the memory cell when the memory cell stores data “0.”
5. The device according to claim 4 , wherein the first isolation gate portion comprises: a first transistor for transmitting a signal between the first bit line and the sense bit line in response to a first isolation control signal; and a second transistor for transmitting a signal between the first bit line and the inverted sense bit line in response to a second isolation control signal.
6. The device according to claim 5 , wherein the second isolation gate portion comprises a third transistor for transmitting a signal between the second bit line and the inverted sense bit line in response to a third isolation control signal.
7. The device according to claim 6 , further comprising a controller for activating the second isolation control signal and applying a sense amplifying voltage during the write operation, for activating the first isolation control signal and the third isolation control signal during the first period of the read operation, for applying first and second sense amplifying voltages during the write operation and during the second period of the read operation, and for activating the second isolation control signal and applying the first and second sense amplifying voltages during the third period of the read operation.
8. The device according to claim 7 , wherein the first sense amplifying voltage is a positive first voltage, and the second sense amplifying voltage is a negative second voltage.
9. The device according to claim 8 , wherein the controller activates the third isolation control signal and applies a third sense amplifying voltage, which is different from the first sense amplifying voltage, during a reference write operation.
10. The device according to claim 9 , wherein the third sense amplifying voltage has a voltage level between the positive first voltage and the negative second voltage.
11. The device according to claim 7 , the precharge operation is performed before and after the write operation, before the first period of the read operation, and after the third period of the read operation.
12. The device according to claim 1 , wherein the precharge portion comprises a third NMOS transistor and a fourth NMOS transistor that are connected in series between the sense bit line and the inverted sense bit line and that precharge the sense bit line and the inverted sense bit line to the precharge voltage level in response to a precharge control signal.
13. A semiconductor memory device comprising: a memory cell array including a first memory cell array block and a second memory cell array block, the first memory cell array block including first memory cells and first reference memory cells, each first memory cell having a floating body connected to a first word line, a first bit line, and a first source line, each first reference memory cell having a floating body connected to a first reference word line, the first bit line, and the first source line, the second memory cell array block including second memory cells and a second reference memory cell, each second memory cell having a floating body connected to a second word line, a second bit line, and a second source line, the second reference memory cell having a floating body connected to a second reference word line, the second bit line, and the second source line; a first isolation gate portion for transmitting a signal between the first bit line and an inverted sense bit line during a first write operation and during a third period of a first read operation, for transmitting a signal between the first bit line and a sense bit line during a first period of the first read operation, and for transmitting a signal between the first bit line and the inverted sense bit line during a third period of a second read operation; a second isolation gate portion for transmitting a signal between the second bit line and the inverted sense bit line during a second write operation and during the third period of the second read operation, for transmitting a signal between the second bit line and the sense bit line during a first period of the second read operation, and for transmitting a signal between the second bit line and the inverted sense bit line during the third period of the first read operation; a precharge portion for precharging the sense bit line and the inverted sense bit line to a precharge voltage level during a precharge operation; and a sense amplifier for amplifying voltages of the sense bit line and the inverted sense bit line to first and second sense amplifying voltage levels during the first and second write operations and during second periods and the third periods of the first and second read operations.
14. The device according to claim 13 , further comprising a column selection gate portion for transmitting data between the sense bit line and a data input/output line, and for transmitting data between the inverted sense bit line and an inverted data input/output line.
15. The device according to claim 13 , wherein the sense amplifier comprises: a PMOS sense amplifier including a first PMOS transistor and a second PMOS transistor that are connected in series between the sense bit line and the inverted sense bit line and that sense high-level data of one of the sense bit line and the inverted sense bit line to amplify the high-level data to the first sense amplifying voltage level; and an NMOS sense amplifier including a first NMOS transistor and a second NMOS transistor that are connected in series between the sense bit line and the inverted sense bit line and that sense low-level data of one of the sense bit line and the inverted sense bit line to amplify the low-level data to the second sense amplifying voltage level.
16. The device according to claim 13 , wherein the precharge portion comprises a third NMOS transistor and a fourth NMOS transistor that are connected in series between the sense bit line and the inverted sense bit line and that precharge the sense bit line and the inverted sense bit line to the precharge voltage level in response to a precharge control signal.
17. The device according to claim 13 , wherein each of the first and second reference memory cells has a threshold voltage that is higher than a threshold voltage of one of the first and second memory cells that stores data “1” and lower than a threshold voltage of one of the first and second memory cells that stores data “0.”
18. The device according to claim 17 , wherein the first isolation gate portion comprises: a first transistor for transmitting a signal between the first bit line and the sense bit line in response to a first isolation control signal; and a second transistor for transmitting a signal between the first bit line and the inverted sense bit line in response to a second isolation control signal.
19. The device according to claim 18 , wherein the second isolation gate portion comprises: a third transistor for transmitting a signal between the second bit line and the sense bit line in response to a third isolation control signal; and a fourth transistor for transmitting a signal between the second bit line and the inverted sense bit line in response to a fourth isolation control signal.
20. The device according to claim 19 , further comprising a controller for activating the second isolation control signal and applying first and second sense amplifying voltages during the first write operation, for activating the first and fourth isolation control signals during the first period of the first read operation, applying the first and second sense amplifying voltages during the second and third periods of the first read operation, and activating the second isolation control signal during the third period of the first read operation, for activating the fourth isolation control signal and applying the first and second sense amplifying voltages during the second write operation, and for activating the second and third isolation control signals during the first period of the second read operation, applying the first and second sense amplifying voltages during the second and third periods of the second read operation, and activating the fourth isolation control signal during the third period of the second read operation.
21. The device according to claim 20 , wherein the first sense amplifying voltage is a positive first voltage, and the second sense amplifying voltage is a negative second voltage.
22. The device according to claim 21 , wherein the controller activates the second isolation control signal and applies a third sense amplifying voltage, which is different from one of the first and second sense amplifying voltages, during a first reference write operation, and activates the fourth isolation control signal and applies the first and third sense amplifying voltages during a second reference write operation.
23. The device according to claim 22 , wherein the third sense amplifying voltage has a voltage level between the positive first voltage and the negative second voltage.
24. The device according to claim 13 , the precharge operation is performed before and after the first and second write operations, before the first period of the first and second read operations, and after the third period of the first and second read operations.
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November 15, 2006
August 10, 2010
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