Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece having a first orientation and at least one second orientation. The semiconductor device is implanted with a dopant species using a first implantation process in the first orientation of the workpiece. The semiconductor device is implanted with the dopant species using a second implantation process in the at least one second orientation of the workpiece, wherein the second implantation process is different than the first implantation process.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a semiconductor chip, the method comprising: providing a workpiece having a first semiconductor device and a second semiconductor device arranged thereon; implanting the semiconductor chip with a dopant species using a first implantation process in a first orientation of the workpiece, wherein the first implantation process comprises implanting the dopant species at a first angle with respect to a top surface of the workpiece; and implanting the semiconductor chip with the dopant species using a second implantation process in at least one second orientation of the workpiece, wherein the second implantation process comprises implanting the dopant species at a second angle with respect to the top surface of the workpiece, wherein the second angle is different than the first angle, and wherein the first semiconductor device comprises different operating parameters than the second semiconductor device.
2. The method according to claim 1 , wherein the first orientation comprises a length of the first and second semiconductor devices, wherein the second orientation comprises a width of the first and second semiconductor devices.
3. The method according to claim 1 , wherein the different implantation processes cause the different operating parameters.
4. The method according to claim 1 , wherein the first semiconductor device comprises a plurality of first semiconductor devices and wherein the second semiconductor device comprises a plurality of second semiconductor devices.
5. The method according to claim 1 , further comprising implanting the semiconductor chip with the dopant species using a third implantation process in the first orientation of the workpiece, wherein the third implantation process comprises implanting the dopant species at a third angle with respect to the top surface of the workpiece, wherein the third angle is different than the first angle.
6. The method according to claim 1 , wherein the first semiconductor device comprises a first transistor and wherein the second semiconductor device comprises a second transistor.
7. A method fabricating a semiconductor chip, the method comprising: providing a workpiece, the workpiece having a first orientation and a second orientation, the workpiece having a first semiconductor device and a second semiconductor device arranged thereon; implanting the semiconductor chip with a dopant species using a first implantation process in the first orientation of the workpiece; and implanting the semiconductor chip with the dopant species using a second implantation process in the at least one second orientation of the workpiece, wherein the first implantation process comprises implanting the dopant species using a first dose, wherein the second implantation process comprises implanting the dopant species using a second dose, wherein the second dose is different than the first dose, and wherein the first semiconductor device comprises different operating parameters than the second semiconductor device.
8. The method according to claim 7 , wherein the first orientation comprises a length of the first and second semiconductor devices and wherein the second orientation comprises a width of the first and second semiconductor devices.
9. The method according to claim 7 , wherein the different implantation processes cause the different operating parameters.
10. The method according to claim 7 , wherein the first semiconductor device comprises a plurality of first semiconductor devices and wherein the second semiconductor device comprises a plurality of second semiconductor devices.
11. The method according to claim 7 , further comprising implanting the semiconductor chip with the dopant species using a third implantation process in the first orientation of the workpiece, wherein the third implantation process comprises implanting the dopant species using a third dose, wherein the third dose is different than the first dose.
12. The method according to claim 7 , wherein the first semiconductor device comprises a first transistor and wherein the second semiconductor device comprises a second transistor.
13. A method of fabricating a semiconductor chip, the method comprising: providing a workpiece, the workpiece having a first orientation and a second orientation, the workpiece having a first semiconductor device and a second semiconductor device arranged thereon; implanting the semiconductor chip with a dopant species using a first implantation process in the first orientation of the workpiece; and implanting the semiconductor chip with the dopant species using a second implantation process in the at least one second orientation of the workpiece, wherein the first implantation process comprises implanting the dopant species at a first energy level, wherein the second implantation process comprises implanting the dopant species at a second energy level, wherein the second energy level is different than the first energy level, and wherein the first semiconductor device comprises different operating parameters than the second semiconductor device.
14. The method according to claim 13 , wherein the first orientation comprises a length of the first and second semiconductor devices and wherein the second orientation comprises a width of the first and second semiconductor devices.
15. The method according to claim 13 , wherein the different implantation processes cause the different operating parameters.
16. The method according to claim 13 , wherein the first semiconductor device comprises a plurality of first semiconductor devices and wherein the second semiconductor device comprises a plurality of second semiconductor devices.
17. The method according to claim 13 , further comprising implanting the semiconductor chip with the dopant species using a third implantation process in the first orientation of the workpiece, wherein the third implantation process comprises implanting the dopant species at a third energy level, wherein the third energy level is different than the first energy level.
18. The method according to claim 13 , wherein the first semiconductor device comprises a first transistor and wherein the second semiconductor device comprises a second transistor.
19. A method of fabricating a semiconductor chip, the method comprising: providing a workpiece, the workpiece having a first orientation and a second orientation, the workpiece having a first semiconductor device and a second semiconductor device arranged thereon; implanting the semiconductor chip with a first dopant species using a first implantation process in the first orientation of the workpiece; and implanting the semiconductor chip with a second dopant species using a second implantation process in the at least one second orientation of the workpiece, the second dopant species being different than the first dopant species, wherein the first semiconductor device comprises different operating parameters than the second semiconductor device.
20. The method according to claim 19 , wherein the first orientation comprises a length of the first and second semiconductor devices and wherein the second orientation comprises a width of the first and second semiconductor devices.
21. The method according to claim 19 , wherein the different implantation processes cause the different operating parameters.
22. The method according to claim 19 , wherein the first semiconductor device comprises a plurality of first semiconductor devices and wherein the second semiconductor device comprises a plurality of second semiconductor devices.
23. The method according to claim 19 , further comprising implanting the semiconductor chip with a third dopant species using a third implantation process in the first orientation of the workpiece, the third dopant species being different than the first and the second dopant species.
24. The method according to claim 19 , wherein the first semiconductor device comprises a first transistor and wherein the second semiconductor device comprises a second transistor.
25. A method of fabricating a semiconductor device, the method comprising: forming a first feature and a second feature in or on a workpiece, the first and the second features all having substantially the same width and substantially the same length; implanting the semiconductor device with a dopant species using a first implantation process in a first direction of the workpiece; and implanting the semiconductor device with the dopant species using a second implantation process in a second direction of the workpiece, wherein the second implantation process comprises a plurality of second parameters, wherein the first implantation process comprises a plurality of first parameters, wherein the plurality of first parameters is different than the plurality of second parameters and wherein the first feature comprises different operating parameters than the second feature.
26. The method according to claim 25 , wherein before implanting the semiconductor device with the dopant species using the first implantation process, the workpiece is oriented in a first position, wherein after implanting the semiconductor device with the dopant species using the first implantation process, the workpiece is rotated about 90 degrees to a second position, and then the semiconductor device is implanted with the dopant species using the second implantation process.
27. The method according to claim 26 , further comprising rotating the workpiece about 90 degrees to a third position, after implanting the semiconductor device with the dopant species using the second implantation process, and then, implanting the semiconductor device with the dopant species using a third implantation process.
28. The method according to claim 25 , wherein the first feature comprises a first transistor and wherein the second feature comprises a second transistor.
29. A method of fabricating a semiconductor device, the method comprising: forming a first feature and a second feature in or on a workpiece, the first and the second features all having substantially a same width and substantially a same length; implanting the semiconductor device with a dopant species using a first implantation process in a first position of the workpiece; rotating the workpiece about 90 degrees to a second position after implanting the semiconductor device with the dopant species using the first implantation process; implanting the semiconductor device with the dopant species using a second implantation process in the second position of the workpiece, wherein the second implantation process comprises a plurality of second parameters, wherein the first implantation process comprises a plurality of first parameters, and wherein the plurality of first parameters is different than the plurality of second parameters; rotating the workpiece about 90 degrees to a third position, after implanting the semiconductor device with the dopant species using the second implantation process; and implanting the semiconductor device with the dopant species using a third implantation process, wherein the third implantation process comprises the same plurality of first parameters as the first implantation process.
30. The method according to claim 29 , further comprising rotating the workpiece about 90 degrees to a fourth position, after implanting the semiconductor device with the dopant species using the third implantation process, and then, implanting the semiconductor device with the dopant species using a fourth implantation process.
31. The method according to claim 30 , wherein the fourth implantation process comprises the same plurality of second parameters as the second implantation process.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 4, 2006
August 17, 2010
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