A multi-phase converter has a plurality of switching circuits each controlled by a phase controller and each providing a switched output voltage to an output node of the converter. Each switching circuit sequentially provides a switched output voltage to the output node at which an output voltage of the converter is developed. A clock circuit provides a plurality of out of phase clock signals to determine when each switching circuit provides the switched voltage to the output node. Each switching circuit is connected across a DC bus voltage. A first error amplifier compares a first signal proportional to the output voltage of the converter at the output node with a second signal comprising a first reference voltage and produces a first error signal. A PWM generator compares the first error signal with a third signal comprising a ramp signal from a ramp signal generator circuit and produces a pulse width modulated signal to control the on-times of a switch of the connected switching circuit. A current share adjusting circuit has a current sense amplifier for each switching circuit sensing the output current provided by each switching circuit, and provides a signal proportional to the sensed output current.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A multi-phase converter comprising: a plurality of switching circuits each controlled by a phase controller and each providing a switched output voltage to an output node of the converter and wherein each switching circuit under control of the phase controller sequentially provides a switched output voltage to the output node at which an output voltage of the converter is developed; a clock circuit for providing a plurality of out of phase clock signals to determine when each switching circuit provides the switched output voltage to the output node; each switching circuit connected across a DC bus voltage, wherein each of said switching circuits further comprises a first error amplifier comparing a first signal proportional to the output voltage of the converter at the output node with a second signal comprising a first reference voltage and producing a first error signal; and a PWM generator circuit comparing said first error signal with a third signal comprising a ramp signal from a ramp signal generator circuit and for producing a pulse width modulated signal to control the on-times of a switch of the connected switching circuit, further comprising a current share adjusting circuit, the current share adjusting circuit comprising: a current sense amplifier for each switching circuit sensing the output current provided by each switching circuit, and providing a signal proportional to the sensed output current; a current share adjust error amplifier having said signal proportional to the sensed output current as a first input and having a signal proportional to an average current provided by each of the switching circuits and for producing a current share adjust signal; and said ramp signal generator circuit producing said ramp signal, said ramp signal generator circuit receiving said current share adjust signal and adjusting the ramp signal to affect the duty cycle of the pulse width modulated signal to move the output current of the connected switching circuit toward the average current.
2. The multi-phase converter of claim 1 , wherein the current share adjust signal adjusts the charge on a capacitor charging from a voltage source such that if the output current of the connected switching circuit is smaller than the average current, the charge on the capacitor is reduced thereby pulling down the starting point of the ramp signal thereby increasing the PWM duty cycle and output current and if the output current of the connected switching circuit is larger than the average current, the charge on the capacitor is increased thereby pulling up the starting point of the ramp signal thereby decreasing the PWM duty cycle and the output current.
3. The multi-phase converter of claim 1 , wherein each switching circuit comprises a buck converter comprising first and second series connected switches connected across the DC bus voltage with a switched node therebetween and having an output inductor coupling the switched node to the converter output node.
4. The multi-phase converter of claim 1 , wherein the phase controllers and the main control circuit are formed as a single integrated circuit.
5. The multi-phase converter of claim 1 , wherein the phase controllers and the main control circuit are separate integrated circuits.
6. The multi-phase converter of claim 1 , wherein the average current signal is produced by providing the output signal of each current sense amplifier to a common node through a resistance.
7. The multi-phase converter of claim 6 , wherein the ramp signal generator circuit comprises a capacitor charged from a voltage source and an amplifier having one input comprising the output of said current share adjust error amplifier and a second input comprising the voltage on said capacitor and wherein said amplifier causes the charge on said capacitor to change to affect the starting point of said ramp signal.
8. The multi-phase converter of claim 7 , wherein said capacitor is coupled to an output of said amplifier by a diode allowing said capacitor to discharge into said amplifier when said diode is forward biased.
9. A phase current adjuster to adjust a phase current of a phase of a multi-phase converter, said phase current adjuster comprising: a first comparison circuit to produce a differential signal based on a comparison of said phase current with an average current of said multi-phase converter; and a ramp comparison circuit configured to adjust said phase current based on a second comparison of said differential signal and a clocked ramp signal.
10. The phase current adjuster of claim 9 , wherein said ramp comparison circuit is further configured to change a duty cycle of a pulse width modulator based on said second comparison of said differential signal and said clocked ramp signal.
11. The phase current adjuster of claim 10 , wherein said ramp comparison circuit is further configured to switch a switch of said pulse width modulator.
12. The phase current adjuster of claim 9 , wherein said ramp comparison circuit is configured to substantially equalize said phase current and said average current.
13. The phase current adjuster of claim 9 , further comprising: a delay circuit comprising a logic circuit connected as part of a daisy-chain configuration to another phase of said multi-phase converter; said delay circuit configured to provide a delayed phase timing to said phase.
14. The phase current adjuster of claim 9 , further comprising a fault latch configured to provide overpower protection to said phase current adjuster.
15. The phase current adjuster of claim 9 , wherein said phase adjuster circuit and said multi-phase converter are packaged on a single semiconductor die.
16. A method for adjusting a phase current of a phase of a multi-phase converter for use by a phase current adjuster, said method comprising: producing a differential signal based on a comparison of said phase current with an average current of said multi-phase converter; and adjusting said phase current based on a second comparison of said differential signal and a clocked ramp signal.
17. The method of claim 16 , further comprising changing a duty cycle of a pulse width modulator based on said second comparison of said differential signal and said clocked ramp signal.
18. The method of claim 17 , wherein said adjusting said phase current further comprises switching a switch of said pulse width modulator.
19. The method of claim 16 , further comprising providing a delayed timing to said phase.
20. The method of claim 16 , further comprising providing overpower protection to said phase current adjuster.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 10, 2007
August 17, 2010
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