Patentable/Patents/US-7781303
US-7781303

Method for preparing a shallow trench isolation

PublishedAugust 24, 2010
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method for preparing a shallow trench isolation comprising the steps of forming at least one trench in a semiconductor substrate, performing an implanting process to implant nitrogen-containing dopants into an upper sidewall of the trench such that the concentration of the nitrogen-containing dopants in the upper sidewall is higher than that in the bottom sidewall of the trench, forming a spin-on dielectric layer filling the trench and covering the surface of the semiconductor substrate, performing a thermal oxidation process to form a silicon oxide layer covering the inner sidewall. Since the nitrogen-containing dopants can inhibit the oxidation rate and the concentration of the nitrogen-containing dopants in the upper inner sidewall is higher than that in the bottom inner sidewall of the trench, the thickness of the silicon oxide layer formed by the thermal oxidation process is larger at the bottom portion than at the upper portion of the trench.

Patent Claims
18 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for preparing a shallow trench isolation, comprising the steps of: forming at least one trench having an inner sidewall in a semiconductor substrate; nitrifying an upper portion of the inner sidewall; forming a spin-on dielectric layer filling the trench and covering the semiconductor substrate; performing a thermal oxidation process to form a silicon oxide layer covering the inner sidewall, wherein the thickness of the silicon oxide layer at a bottom portion is larger than at the upper portion of the trench; and forming a liner layer on the inner sidewall before the step of nitrifying an upper portion of the inner sidewall.

2

2. The method for preparing a shallow trench isolation of claim 1 , wherein the step of forming a liner layer on the inner sidewall includes performing a thermal oxidation process.

3

3. The method for preparing a shallow trench isolation of claim 1 , wherein the liner layer is a silicon oxide layer.

4

4. The method for preparing a shallow trench isolation of claim 1 , wherein the step of nitrifying an upper portion of the inner sidewall includes performing a tilt implanting process to implant nitrogen-containing dopants into the upper portion of the inner sidewall.

5

5. The method for preparing a shallow trench isolation of claim 4 , wherein the nitrogen-containing dopants are ions selected from a group consisting of nitrogen atom, nitrogen gas, nitrous oxide and nitric oxide.

6

6. The method for preparing a shallow trench isolation of claim 1 , wherein the step of nitrifying an upper portion of the inner sidewall includes performing a plasma immersion process to implant nitrogen-containing dopants into the upper portion of the inner sidewall.

7

7. The method for preparing a shallow trench isolation of claim 6 , wherein the nitrogen-containing dopants are ions selected from a group consisting of nitrogen atom, nitrogen gas, nitrous oxide and nitric oxide.

8

8. The method for preparing a shallow trench isolation of claim 1 , wherein the thermal oxidation process solidifies the spin-on dielectric layer by removing solvent from the spin-on dielectric layer.

9

9. The method for preparing a shallow trench isolation of claim 1 , wherein the step of forming at least one trench having an inner sidewall in a semiconductor substrate comprises: forming a mask having at least one opening on the semiconductor substrate; performing an anisotropic etching process to remove a portion of the semiconductor substrate from the opening to form the trench in the semiconductor substrate.

10

10. A method for preparing a shallow trench isolation, comprising the steps of: forming at least one trench having an inner sidewall in a semiconductor substrate; performing an implanting process to implant nitrogen-containing dopants into the inner sidewall; forming a spin-on dielectric layer filling the trench; performing a thermal oxidation process to form a silicon oxide layer covering the inner sidewall, wherein the thickness of the silicon oxide layer at a bottom portion is larger than at an upper portion of the trench; and forming a liner layer on the inner sidewall before the step of performing an implanting process to implant nitrogen-containing dopants into the inner sidewall.

11

11. The method for preparing a shallow trench isolation of claim 10 , wherein the step of forming a liner layer on the inner sidewall includes performing a thermal oxidation process.

12

12. The method for preparing a shallow trench isolation of claim 10 , wherein the liner layer is a silicon oxide layer.

13

13. The method for preparing a shallow trench isolation of claim 10 , wherein the implanting process is a tilt implanting process to implant nitrogen-containing dopants into the upper portion of the inner sidewall.

14

14. The method for preparing a shallow trench isolation of claim 13 , wherein the nitrogen-containing dopants are ions selected from a group consisting of nitrogen atom, nitrogen gas, nitrous oxide and nitric oxide.

15

15. The method for preparing a shallow trench isolation of claim 10 , wherein the implanting process is a plasma immersion process to implant nitrogen-containing dopants into the upper portion of the inner sidewall.

16

16. The method for preparing a shallow trench isolation of claim 15 , wherein the nitrogen-containing dopants are ions selected from a group consisting of nitrogen atom, nitrogen gas, nitrous oxide and nitric oxide.

17

17. The method for preparing a shallow trench isolation of claim 10 , wherein the concentration of the nitrogen-containing dopants at the upper portion is higher than that at the bottom portion of the trench.

18

18. The method for preparing a shallow trench isolation of claim 10 , wherein the step of forming at least one trench having an inner sidewall in a semiconductor substrate comprises: forming a mask having at least one opening on the semiconductor substrate; performing an anisotropic etching process to remove a portion of the semiconductor substrate from the opening to form the trench in the semiconductor substrate.

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Patent Metadata

Filing Date

July 9, 2007

Publication Date

August 24, 2010

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