In one embodiment, a soft start circuit includes a slew rate controller to limit inrush current to a voltage regulator during start up. The output voltage of the regulator may be compared to a previous sampled value to determine the slew rate of the output voltage. The slew rate of the output voltage may be controlled by adjusting the current limit of the regulator. The current limit of the regulator may be adjusted using digital circuits, such as a counter and a digital to analog converter, or analog circuits using a pulsed current source, for example. The slew rate may be controlled to exceed a target slew rate or to stay within a range of slew rate limits.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of controlling a slew rate of a voltage regulator during start up, the method comprising: measuring a slew rate of an output voltage of a voltage regulator to get a detected slew rate value during startup of the regulator from a power OFF state; determining the slew rate by comparing the output voltage to a sampled value of the output voltage taken at a previous pulse width modulation (PWM) regulation cycle; and adjusting the current limit of the regulator to control the slew rate based on the detected slew rate value during start up.
2. The method of claim 1 wherein monitoring the slew rate of the regulator comprises: sampling the output voltage at a first PWM regulation cycle to get a first output voltage value; sampling the output voltage at a second PWM regulation cycle immediately following the first PWM regulation cycle to get a second output voltage value; and comparing the first output voltage value to the second output voltage value to determine the slew rate.
3. The method of claim 1 wherein adjusting the current limit of the regulator comprises: increasing the current limit of the regulator to increase the slew rate.
4. The method of claim 3 wherein increasing the current limit of the regulator comprises: incrementing a counter; inputting a count output of the counter to a digital to analog converter (DAC) that generates a current limit reference signal based on the count output; and using the current limit reference signal generated by the DAC to set the current limit of the regulator.
5. The method of claim 3 wherein increasing the current limit of the regulator comprises: charging a capacitor that provides a current limit reference to the regulator.
6. The method of claim 5 wherein the capacitor is charged by a current source that sends a pulsed signal to the capacitor when the slew rate is below a target slew rate.
7. The method of claim 1 wherein adjusting the current limit of the regulator comprises: decreasing the current limit of the regulator to decrease the slew rate.
8. The method of claim 1 wherein the current limit of the regulator is not adjusted when the slew rate is within a target slew rate.
9. The method of claim 1 further comprising: releasing control of the current limit of the regulator after the start up.
10. The method of claim 9 wherein releasing control of the current limit of the regulator comprises setting the current limit to its maximum operational value.
11. An electrical circuit comprising: a first circuit configured to determine a slew rate of an output voltage of a voltage regulator during a start up of the regulator by comparing the output voltage to a sampled value of the output voltage taken at a previous pulse width modulation (PWM) regulation cycle; and a second circuit configured to adjust a current limit of the regulator to control the slew rate during start up, the second circuit adjusting the current limit based on the slew rate determined by the first circuit.
12. The electrical circuit of claim 11 wherein the first circuit comprises: a sampling circuit configured to couple the output to a capacitor for sampling; and a first comparator configured to compare the output to a previous sampled value of the output.
13. The electrical circuit of claim 12 wherein the first circuit further comprises: a second comparator configured to compare the output to the previous sampled value of the output to determine if the slew rate exceeds a maximum slew rate limit.
14. The electrical circuit of claim 11 wherein the second circuit comprises: a counter having a count configured to increment when the slew rate is below a target slew rate; and a digital to analog converter configured to output a current limit reference for adjusting the limit of the regulator based on the count of the counter.
15. The electrical circuit of claim 14 wherein the counter is further configured to decrement when the slew rate is above a maximum slew rate limit.
16. The electrical circuit of claim 11 wherein the voltage regulator comprises a hysteretic voltage regulator.
17. A method of controlling a slew rate of a voltage regulator during start up, the method comprising: setting a current limit of a voltage regulator to a first current limit value during a start up sequence of the regulator; measuring a slew rate of an output voltage of the regulator by comparing the output voltage to a sampled value of the output voltage taken at a previous pulse width modulation regulation cycle; and using the measured slew rate to determine whether to adjust the current limit during the start up.
18. The method of claim 17 further comprising: increasing the current limit from the first current limit value to a higher second current limit value when the measured slew rate is below a target slew rate.
19. The method of claim 17 further comprising: decreasing the current limit from the first current limit value to a lower second current limit value when the measured slew rate is above a target slew rate.
20. The method of claim 17 wherein the first current limit value is an initial current limit value set at a beginning of the start up sequence.
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March 23, 2007
August 24, 2010
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