Adaptive mismatch compensators and methods for mismatch compensation

1. A mismatch compensator that compensates for mismatches in output signals of a system with mismatches during normal operation of the system with mismatches, comprising: a mismatch estimator that monitors at least two mismatched signals output by the system with mismatches during normal operation and that generates matching parameters indicating an amount of mismatch between the at least two mismatched signals, the mismatch estimator updating the matching parameters during normal operation of the system with mismatches; and a mismatch equalizer that compensates mismatches in the mismatched signals output by the system with mismatches during normal operation of the system with mismatches in response to the matching parameters.

2. The mismatch compensator of claim 1 wherein the mismatch estimator continually monitors the at least two mismatched signals output by the system with mismatches and continually updates the matching parameters during normal operation of the system with mismatches, and wherein the mismatch equalizer adaptively compensates mismatches in the mismatched signals output by the system with mismatches during normal operation of the system with mismatches.

3. The mismatch compensator of claim 1 wherein the matching parameters comprise at least one of: a DC-offset parameter, a gain parameter, and a phase shift parameter.

4. The mismatch compensator of claim 1 wherein the mismatch equalizer compensates for mismatches in at least two mismatched signals as a function of frequency.

5. The mismatch compensator of claim 1 wherein the mismatch equalizer comprises: a coefficient generator that receives the matching parameters and generates filter coefficients; a plurality of digital signal processors that compensate for gain and phase mismatches in response to the filter coefficients.

6. The mismatch compensator of claim 1 wherein the mismatch estimator comprises at least one of: a gain estimator that calculates gain estimates of the at least two mismatched signals output by the system with mismatches; a phase estimator that calculates phase estimates of the at least two mismatched signals output by the system with mismatches; and a DC-offset estimator that calculates DC-offset estimates of the at least two mismatched signals output by the system with mismatches; and wherein the mismatch estimator generates the matching parameters in response to at least one of the gain estimates, the phase estimates and the DC-offset estimates.

7. The mismatch compensator of claim 6 wherein the mismatch estimator further comprises a cataloger that stores histories of at least one of the gain estimates, the phase estimates and the DC-offset estimates, and that heuristically processes the stored estimates to generate the matching parameters.

8. The mismatch compensator of claim 7 wherein the cataloger further stores histories of at least one of time, temperature and mode of operation information of the system with mismatches and heuristically processes the stored estimates and information to generate the matching parameters.

9. The mismatch compensator of claim 6 wherein the mismatch estimator further comprises: a channelizer that partitions each of the at least two mismatched signals output by the system with mismatches into channelized signals in response to a channel select signal wherein the channelized signals represent a selected frequency subband of the unmatched output signals of the system with mismatches; wherein the gain estimator calculates gain estimates of the channelized signals, wherein the phase estimator calculates phase estimates of the channelized signals, and wherein the DC-offset estimator calculates DC-offset estimates of the channelized signals.

10. The mismatch compensator of claim 9 wherein the phase estimator comprises: a plurality of variable phase shifters that adjust phases of the channelized signals in response to variable phase shift signals and generates phase shifted signals; a plurality of subtractors that subtract the phase shifted signals of respective variable phase shifters to generate difference signals; a plurality of level estimators that calculate the magnitudes of the difference signals and that generate phase difference signals; and a phase processor that processes the phase difference signals and generates phase estimate signals.

11. The mismatch compensator of claim 10 wherein the phase processor processes the phase difference signals and generates the variable phase shift signals using an iterative optimization and generates the phase estimate signals.

12. The mismatch compensator of claim 10 wherein the level estimators generate phase difference signals by a running average of the squared amplitude of each of the difference signals.

13. The mismatch compensator of claim 9 wherein the mismatch estimator comprises: a gain and phase estimator that calculates gain estimates and phase estimates of the channelized signals.

14. The mismatch compensator of claim 13 wherein the gain and phase estimator comprises: a plurality of variable gain and phase shifters that adjust gains and phases of the channelized signals in response to variable gain and phase shift signals and generates gain and phase shifted signals; a plurality of subtractors that subtract the gain and phase shifted signals of respective variable gain and phase shifters to generate difference signals; a plurality of cancellation estimators that calculate the magnitude of the vector cancellation of the difference signals and that generate vector cancellation level signals; and a gain and phase processor that processes the vector cancellation level signals and generates gain and phase estimate signals.

15. The mismatch compensator of claim 14 wherein the gain and phase processor processes the vector cancellation level signals and generates variable gain and phase shift signals using an iterative optimization and generates the gain and phase estimate signals.

16. The mismatch compensator of claim 13 wherein the gain and phase estimator comprises: a plurality of variable phase shifters that adjust a phase of the channelized signals in response to variable phase shift signals and generates phase shifted signals; a plurality of background calibration sequence level estimators that calculate the magnitude of the background calibration sequence signal to generate calibration sequence level signals; and a background calibration sequence processor that processes the calibration level sequence signals and generates gain and phase estimate signals.

17. The mismatch compensator of claim 16 wherein the background calibration sequence processor processes the calibration level sequence signals and generates variable phase shift signals using an iterative optimization and generates gain and phase estimate signals.

18. An analog-to-digital converter system that compensates for mismatches in converted digital signals during normal operation of the analog-to-digital converter system, comprising: a plurality of analog-to-digital converters, each converting an analog input signal to a converted digital signal, the converted digital signals having mismatches; a mismatch estimator that monitors at least two mismatched converted digital signals output by the analog-to-digital converters during normal operation and that generates matching parameters indicating an amount of mismatch between the at least two mismatched converted digital signals, the mismatch estimator updating the matching parameters during normal operation of the analog-to-digital converter system; and a mismatch equalizer that compensates mismatches in the mismatched converted digital signals output by the analog-to-digital converters during normal operation of the analog-to-digital converter system in response to the matching parameters.

19. The analog-to-digital converter system of claim 18 wherein the mismatch estimator continually monitors the at least two mismatched converted digital signals output by the analog-to-digital converters and continually updates the matching parameters during normal operation of the analog-to-digital converter system, and wherein the mismatch equalizer adaptively compensates mismatches in the mismatched signals output by the analog-to-digital converters during normal operation of the analog-to-digital converter system.

20. The analog-to-digital converter system of claim 18 wherein the matching parameters comprise at least one of: a DC-offset parameter, a gain parameter, and a phase shift parameter.

21. The analog-to-digital converter system of claim 18 wherein the mismatch equalizer compensates for mismatches in at least two mismatched signals as a function of frequency.

22. The analog-to-digital converter system of claim 18 wherein the mismatch equalizer comprises: a coefficient generator that receives the matching parameters and generates filter coefficients; and a plurality of digital signal processors that compensate for gain and phase mismatches in response to the filter coefficients.

23. The analog-to-digital converter system of claim 18 wherein the mismatch estimator comprises at least one of: a gain estimator that calculates gain estimates of the at least two mismatched signals output by the analog-to-digital converters; a phase estimator that calculates phase estimates of the at least two mismatched signals output by the analog-to-digital converters; and a DC-offset estimator that calculates DC-offset estimates of the at least two mismatched signals output by the analog-to-digital converters; and wherein the mismatch estimator generates the matching parameters in response to at least one of the gain estimates, the phase estimates and the DC-offset estimates.

24. The analog-to-digital converter system of claim 23 wherein the mismatch estimator further comprises a cataloger that stores histories of at least one of the gain estimates, the phase estimates and the DC-offset estimates, and that heuristically processes the stored estimates to generate the matching parameters.

25. The analog-to-digital converter system of claim 24 wherein the cataloger further stores histories of at least one of time, temperature and mode of operation information of the system with mismatches and heuristically processes the stored estimates and information to generate the matching parameters.

26. The analog-to-digital converter system of claim 23 wherein the mismatch estimator further comprises: a channelizer that partitions each of the at least two mismatched signals output by the analog-to-digital converters into channelized signals in response to a channel select signal wherein the channelized signals represent a selected frequency subband of the unmatched output signals of the analog-to-digital converters; wherein the gain estimator calculates gain estimates of the channelized signals, wherein the phase estimator calculates phase estimates of the channelized signals, and wherein the DC-offset estimator calculates DC-offset estimates of the channelized signals.

27. The analog-to-digital converter system of claim 26 wherein the phase estimator comprises: a plurality of variable phase shifters that adjust phases of the channelized signals in response to variable phase shift signals and generates phase shifted signals; a plurality of subtractors that subtract the phase shifted signals of respective variable phase shifters to generate difference signals; a plurality of level estimators that calculate the magnitudes of the difference signals and that generate phase difference signals; and a phase processor that processes the phase difference signals and generates phase estimate signals.

28. The analog-to-digital converter system of claim 27 wherein the phase processor processes the phase difference signals and generates the variable phase shift signals using an iterative optimization and generates phase estimate signals.

29. The analog-to-digital converter system of claim 27 wherein the level estimators generate phase difference signals by a running average of the squared amplitude of each of the difference signals.

30. The analog-to-digital converter system of claim 26 wherein the mismatch estimator comprises: a gain and phase estimator that calculates gain estimates and phase estimates of the channelized signals.

31. The analog-to-digital converter system of claim 30 wherein the gain and phase estimator comprises: a plurality of variable gain and phase shifters that adjust gains and phases of the channelized signals in response to variable gain and phase shift signals and generates gain and phase shifted signals; a plurality of subtractors that subtract the gain and phase shifted signals of respective variable gain and phase shifters to generate difference signals; a plurality of cancellation estimators that calculate the magnitude of the vector cancellation of the difference signals and that generate vector cancellation level signals; and a gain and phase processor that processes the vector cancellation level signals and generates gain and phase estimate signals.

32. The analog-to-digital converter system of claim 31 wherein the gain and phase processor processes the vector cancellation level signals and generates variable gain and phase shift signals using an iterative optimization and generates the gain and phase estimate signals.

33. The analog-to-digital converter system of claim 30 wherein the gain and phase estimator comprises: a plurality of variable phase shifters that adjust a phase of the channelized signals in response to variable phase shift signals and generates phase shifted signals; a plurality of background calibration sequence level estimators that calculate the magnitude of the background calibration sequence signal to generate calibration sequence level signals; and a background calibration sequence processor that processes the calibration level sequence signals and generates gain and phase estimate signals.

34. The analog-to-digital converter system of claim 33 wherein the background calibration sequence processor processes the calibration level sequence signals and generates variable phase shift signals using an iterative optimization and generates gain and phase estimate signals.

35. A multi-stage analog-to-digital converter that compensates for mismatches in signals during normal operation, comprising: a first analog-to-digital converter that converts an analog input signal into a corresponding first stage digital signal; an analog delay unit that delays the analog input signal to generate a delayed analog input signal; a first mismatch equalizer that compensates mismatches between the delayed analog input signal and a first stage analog signal during normal operation of the multi-stage analog-to-digital converter in response to first matching parameters and that outputs a first stage matched digital signal; a first digital-to-analog converter that converts the first stage matched digital signal to the first stage analog signal; a subtractor that subtracts the delayed analog input signal from the first stage analog signal to generate a residual analog signal; a second analog-to-digital converter that converts the residual analog signal into a corresponding second stage digital signal; a second mismatch equalizer that compensates mismatches between the first stage digital signal and the second stage digital signal output by the second analog-to-digital converter during normal operation of the multi-stage analog-to-digital converter in response to second matching parameters and that outputs a second stage matched digital signal; and a mismatch estimator that monitors the second stage digital signal during normal operation of the multi-stage analog-to-digital converter and that generates the first matching parameters indicating an amount of mismatch between the delayed analog input signal and the first stage analog signal and that generates the second matching parameters indicating an amount of mismatch between the first stage digital signal and the second stage digital signal, the mismatch estimator updating the first and second matching parameters during normal operation of the multi-stage analog-to-digital converter.

36. A method of compensating for mismatches in output signals of a system with mismatches during normal operation of the system with mismatches, comprising: monitoring at least two mismatched signals output by the system with mismatches during normal operation and generating matching parameters indicating an amount of mismatch between the at least two mismatched signals, the mismatch estimator updating the matching parameters during normal operation of the system with mismatches; and compensating mismatches in the mismatched signals output by the system with mismatches during normal operation of the system with mismatches in response to the matching parameters.

37. A method for compensating mismatches in a system with mismatches, the method comprising: monitoring at least two mismatched signals output by the system with mismatches; determining amplitudes of the at least two mismatched signals; determining frequency content of the at least two mismatched signals; and during normal operation of the system with mismatches, determining whether the at least two mismatched signals are suitable for an accurate estimation of at least one of: gain mismatch, phase mismatch, and DC-offset based on the determined amplitudes and frequency content of the at least two mismatched signals; and during normal operation of the system with mismatches, estimating at least one of the gain mismatch, the phase mismatch, and the DC-offset between the at least two mismatched signals; compensating for mismatches in the at least two mismatched signals based on the estimated at least one of the gain mismatch, the phase mismatch, and the DC-offset between the at least two mismatched signals.