Memory control circuit and semiconductor device

1. A semiconductor device, comprising: a plurality of switching transistors configured to perform trimming for characteristic adjustment of the semiconductor device; and a nonvolatile memory connected to the plural switching transistors and configured to store data for determining ON and OFF of the plural switching transistors; wherein when the semiconductor device is in operation, ON and OFF of the switching transistors are determined by the data.

2. A memory control circuit used for semiconductor device including a plurality of switching transistors configured to perform trimming for characteristic adjustment of the semiconductor device and a nonvolatile memory connected to the switching transistors and configured to store data for determining ON and OFF of the plural switching transistors, the ON and OFF of the plural switching transistors being determined by the data when the semiconductor device is in operation, the memory control circuit comprising: a test terminal; and a shift register connected to the test terminal and the nonvolatile memory; wherein one or more bits of the shift register are used as a mode switching flag for switching between a data input mode of inputting data to be written into the nonvolatile memory, and a high voltage application mode of writing data into the nonvolatile memory, and the input of data to be written into the nonvolatile memory, input of data transfer clock, and the high voltage application for writing data into the nonvolatile memory are performed by using the test terminal.

3. The memory control circuit as claimed in claim 2 , wherein one or more bits of the nonvolatile memory are used as flag bits for starting a mode of writing data into the nonvolatile memory, immediately after the semiconductor device is powered ON or a chip-enabled terminal of the semiconductor device is active, data stored in the nonvolatile memory is read out, when data are not written in the flag bits, the mode of writing in the nonvolatile memory starts, and when data are written in the flag bits, writing in the nonvolatile memory starts is not performed.

4. The memory control circuit as claimed in claim 3 , wherein one or more bits of the nonvolatile memory are set to be writable, and other one or more bits of the nonvolatile memory are set to be un-writable, immediately after the semiconductor device is powered ON or the chip-enabled terminal of the semiconductor device is active, the reading out of the data stored in the nonvolatile memory continues until both the writable bits and the un-writable bits are read out.

5. The memory control circuit as claimed in claim 2 , wherein the shift register further includes a bit indicating an address in the nonvolatile memory, and a bit indicating data to be written in the nonvolatile memory, a bit indicating an address in the nonvolatile memory, and the one or more bits as the mode switching flag.

6. The memory control circuit as claimed in claim 2 , further includes a Vpp switching circuit that detects that the mode switching flag becomes 1, indicating that data required by the shift register has been input, and set the test terminal to be in the high voltage application mode.