Patentable/Patents/US-7786607
US-7786607

Overlay correction by reducing wafer slipping after alignment

PublishedAugust 31, 2010
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method and apparatus for correcting overlay errors in a lithography system. During lithographic exposure, features being exposed on the wafer need to overlay existing features on the wafer. Overlay is a critical performance parameter of lithography tools. The wafer is locally heated during exposure. Thermal expansion causes stress between the wafer and the wafer table, which will cause the wafer to slip if it exceeds the local frictional force. To increase the amount of expansion allowed before slipping occurs, the wafer chuck is uniformly expanded after the wafer has been loaded. This creates an initial stress between the wafer and the wafer table. As the wafer expands due to heating during exposure, the expansion first acts to relieve the initial stress before causing an opposite stress from thermal expansion. The wafer may be also be heated prior to attachment to the wafer chuck, creating the initial stress as the wafer cools.

Patent Claims
16 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A wafer alignment system, comprising: a wafer chuck configured to receive a wafer; and an expandable annular tube coupled to the wafer chuck and configured to expand the wafer chuck without substantially expanding the wafer to reduce wafer slipping, such that an initial stress at an interface between the wafer and the wafer chuck is created, wherein said annular tube having an outer surface which is coupled to an outer edge of the wafer chuck such that the outer surface of said annular tube is substantially outside of the wafer chuck to uniformly expand the wafer chuck.

2

2. The system of claim 1 , wherein said annular tube comprises a metal.

3

3. The system of claim 1 , wherein said annular tube comprises a plastic.

4

4. The system of claim 1 , wherein said annular tube includes a cavity, and wherein the cavity is configured to be filled with one of a gas and a liquid.

5

5. The system of claim 1 , further comprising: a temperature sensor coupled to the wafer chuck.

6

6. The system of claim 1 , wherein said wafer chuck is configured to releasably secure or hold the wafer by vacuum clamping.

7

7. The system of claim 1 , wherein said wafer chuck is configured to releasably secure or hold the wafer by electrostatic clamping.

8

8. The system of claim 1 , wherein said annular tube is sealed to be pressurized and configured to expand to in turn expand the wafer chuck when pressurized.

9

9. A wafer alignment system, comprising: a wafer stage; a wafer chuck configured to receive a wafer; and an expandable annular tube coupled to the wafer chuck and configured to uniformly expand the wafer chuck prior to exposure without substantially expanding the wafer to provide an overlay correction by reducing wafer slipping during the exposure after the wafer has been aligned to the wafer stage, such that an initial stress at an interface between the wafer and the wafer chuck is created, wherein said annular tube is a sealed tube that includes a cavity which is disposed along the circumference of the wafer chuck.

10

10. The wafer alignment system of claim 9 , wherein said annular tube comprises a metal.

11

11. The wafer alignment system of claim 9 , wherein said annular tube comprises a plastic.

12

12. The wafer alignment system of claim 9 , wherein said cavity is configured to be filled with one of a gas and a liquid.

13

13. The wafer alignment system of claim 9 , further comprising: a temperature sensor coupled to the wafer chuck.

14

14. The wafer alignment system of claim 9 , wherein the wafer chuck is configured to releasably secure or hold the wafer by vacuum clamping.

15

15. The wafer alignment system of claim 9 , wherein the wafer chuck is configured to releasably secure or hold the wafer by electrostatic clamping.

16

16. The wafer alignment system of claim 9 , wherein said sealed tube is sealed to be pressurized and configured to expand to in turn expand the wafer chuck when pressurized.

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Patent Metadata

Filing Date

February 19, 2004

Publication Date

August 31, 2010

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Cite as: Patentable. “Overlay correction by reducing wafer slipping after alignment” (US-7786607). https://patentable.app/patents/US-7786607

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