A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A discrete time analog filter comprising a cascade of single pole analog IIR filters configured to generate an output signal in response to an input signal.
2. The discrete time analog filter according to claim 1 , further comprising means for direct sampling, wherein the cascade of single pole IIR filters and means for direct sampling together implement a high order filter devoid of amplifiers.
3. The discrete time analog filter according to claim 1 , wherein the cascade of single pole IIR filters together implement a high order filter devoid of amplifiers.
4. The discrete time analog filter according to claim 1 , wherein the cascade of single pole IIR filters is operational to create a uni-directional flow of information, signal, or charge and disallow any feedback from a later filter stage to an earlier filter stage.
5. A discrete time analog filter comprising: a cascade of single pole analog IIR filters configured to generate an output signal in response to an input signal; and a multi-tap direct sampling mixer, wherein the cascade of single pole IIR filters and multi-tap direct sampling mixer together implement a high order filter devoid of amplifiers.
6. A discrete time analog filter comprising: a cascade of single pole analog IIR filters configured to generate an output signal in response to an input signal, wherein the cascade of single pole IIR filters together implement a high order filter devoid of amplifiers, and comprises a history capacitor that is charged together with a first rotating capacitor in a first capacitor bank for a predetermined time period while a charge in a second capacitor bank is charge shared with a buffer capacitor and a second rotating capacitor, and wherein during a subsequent time period, the first capacitor bank holding its charge is charge shared with the buffer capacitor while the second capacitor bank which was charge shared in a previous time period now collects new samples together with the history capacitor.
7. The discrete time analog filter according to claim 6 , wherein the charge on the second rotating capacitor is reset only after it charge shares with the buffer capacitor on the following stage and before it obtains a new sample from the preceding stage.
8. A discrete time analog filter comprising: a cascade of single pole analog IIR filters configured to generate an output signal in response to an input signal; a comparator responsive to the filter output signal to generate an output signal there from; and a negative feedback loop enclosing the cascade of single pole IIR filters and the comparator such that the input signal consists of an RF input signal combined with a negative feedback signal flowing in the negative feedback loop.
9. The discrete analog filter according to claim 8 , wherein the cascade of single pole IIR filters together operate as a loop filter inside a sigma delta loop.
10. The discrete analog filter according to claim 8 , wherein the input signal consists of an RF input signal minus a negative feedback signal flowing in the negative feedback loop.
11. The discrete analog filter according to claim 8 , wherein the comparator comprises an ADC.
12. The discrete analog filter according to claim 11 , wherein the ADC comprises a multi-bit flash ADC.
13. The discrete analog filter according to claim 8 , wherein the negative feedback loop comprises a digital-to-analog converter (DAC).
14. A receiver front-end comprising a cascade of single pole IIR analog filters configured to generate an output signal in response to an input signal.
15. A receiver front-end comprising: a cascade of single pole IIR analog filters configured to generate an output signal in response to an input signal; and a means for direct sampling, wherein the cascade of single pole IIR filters and means for direct sampling together implement a high order filter devoid of amplifiers.
16. A receiver front-end comprising: a cascade of single pole analog IIR filters configured to generate an output signal in response to an input signal; and a multi-tap direct sampling mixer, wherein the cascade of single pole IIR filters and multi-tap direct sampling mixer together implement a high order filter devoid of amplifiers.
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March 24, 2006
September 7, 2010
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