A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory comprising: an array of memory cells arranged in N rows of memory cells and M columns of memory cells; M write select lines coupling to corresponding columns of memory cells; N write data lines coupling to corresponding rows of memory cells; a write address decoder adapted to enable a selected one of the write select lines in response to a write address; and N gating circuits, each gating circuit adapted to selectively assert a data signal or an inhibit signal to a corresponding one of the write data lines in response to a corresponding write select signal; wherein each data signal has a value, and wherein at least one of the memory cells is adapted, when a corresponding write select line is enabled, to store the data signal value when the data signal is present on a corresponding write data line and to retain the data stored therein when the inhibit signal is present on the corresponding write data line, and wherein each of the write data lines comprises a pair of conductors, each gating circuit being adapted to assert one of two logic values on each conductor of the pair of conductors of a corresponding write data line to form logic value combinations thereon, the data signal on a write data line being at least one of a first group of the logic value combinations, and the inhibit signal on the write data line being at least one of a second group of the logic value combinations, the first group of the logic value combinations being different from the second group of the logic value combinations.
2. The memory of claim 1 , further comprising: M read select lines coupling to corresponding columns of memory cells; N bit lines coupling to corresponding rows of memory cells; and a read address decoder adapted to enable a selected one of the read select lines in response to a read address; wherein data stored in a column of memory cells is coupled to corresponding bit lines in response to the enabled read select line.
3. The memory of claim 1 , further comprising: an N-bit write select register adapted to generate the write select signals.
4. The memory of claim 1 , wherein the data signal and the inhibit signal have a low impedance.
5. The memory of claim 1 , wherein having same logic values on each conductor of the pair of conductors is the first group of the logic value combinations and having different logic values on each conductor of the pair of conductors is the second group of the logic value combinations.
6. The memory of claim 5 , wherein each memory cell in the array of memory cells comprises: a bistable latch having an input; a first switch adapted to selectively couple a node to the input of the bistable latch when the corresponding write select line is enabled; a first transistor having a control terminal coupled to a first conductor of the pair of conductors of the corresponding write data line, a first output terminal coupled to the node, and a second output terminal coupled to a first voltage node; and a second transistor having a control terminal coupled to a second conductor of the pair of conductor of the corresponding write data line, a first output terminal coupled to the node, and a second output terminal coupled to a second voltage node.
7. The memory of claim 6 , wherein the memory further comprises: M read select lines coupling to corresponding columns of memory cells; N bit lines coupling to corresponding rows of memory cells; and a read address decoder adapted to enable a selected one of the read select lines in response to a read address; wherein for each memory cell of the array of memory cells the bistable latch has an output, and wherein each of the memory cells of the array of memory cells further comprises: a second switch adapted to couple the output of the bistable latch to a corresponding bit line when a corresponding read select line is enabled.
8. The memory of claim 7 , wherein the bistable latch comprises cross-coupled inverters, the first and second transistors are MOS transistors, the first and second switches are transmission gates, the first voltage node is a ground node, and the second voltage node is a power supply node.
9. The memory of claim 6 , wherein bistable latch comprises cross-coupled inverters, one of the inverters being weaker than the other, the weaker inverter having an output coupled to the input of the bistable latch.
10. The memory of claim 5 , wherein each memory cell comprises: a bistable latch having an input; a first pair of series-coupled transistors coupled between a first voltage node and the input of the bistable latch, one transistor of the first pair of transistors having a control terminal coupled to a first conductor of the pair of conductors of a corresponding write data line and the other transistor of the first pair of transistors having a control terminal coupled to the corresponding write select line; and a second pair of series-coupled transistors coupled between a second voltage node and the input of the bistable latch, one transistor of the second pair of transistors having a control terminal coupled to a second conductor of the pair of conductors the corresponding write data line and the other transistor of the second pair of transistors having a control terminal coupled to the corresponding write select line.
11. The memory of claim 10 , wherein the memory further comprises: M read select lines coupling to corresponding columns of memory cells; N bit lines coupling to corresponding rows of memory cells; and a read address decoder adapted to enable a selected one of the read select lines in response to a read address; wherein for each memory cell of the array of memory cells the bistable latch has an output, and wherein each of the memory cells of the array of memory cells further comprises: a switch adapted to couple the output of the bistable latch to a corresponding bit line when a corresponding read select line is enabled.
12. The memory of claim 11 , wherein the bistable latch comprises cross-coupled inverters, first and second pairs of series-coupled transistors are MOS transistors, the switch is a transmission gate, the first voltage node is a ground node, and the second voltage node is a power supply node.
13. The memory of claim 10 , wherein the bistable latch comprises cross-coupled inverters, one of the inverters being weaker than the other, the weaker inverter having an output coupled to the input of the bistable latch.
14. The memory of claim 10 , wherein the bistable latch further comprises an inverter disposed between the corresponding write select line and the control terminal of the second pair of transistors coupling to the corresponding write select line.
15. A memory comprising: an array of memory cells arranged in N rows of memory cells and M columns of memory cells; M write select lines coupling to corresponding columns of memory cells; N write data lines coupling to corresponding rows of memory cells, each of the write data lines comprising a pair of conductors; M read select lines coupling to corresponding columns of memory cells; N bit lines coupling to corresponding rows of memory cells; a write address decoder adapted to enable a selected one of the write select lines in response to a write address; a read address decoder adapted to enable a selected one of the read select lines in response to a read address; N gating circuits, each gating circuit in response to a corresponding write select signal is adapted to selectively assert a data signal having same logic values on each conductor of the pair of conductors of a corresponding write data line, or an inhibit signal having different logic values on each conductor of the pair of conductors of the corresponding write data line; wherein each data signal has a value, and wherein at least one of the memory cells is adapted, when a write select line corresponding to the at least one memory cell is enabled, to store the data signal value when the data signal is present on a corresponding write data line and to retain the data stored therein when the inhibit signal is present on the write data line corresponding to the at least one memory cell.
16. The memory of claim 15 , wherein each memory cell in the array of memory cells comprises: a bistable latch having an input and an output; a first switch adapted to selectively couple a node to the input of the bistable latch when the corresponding write select line is enabled; a first transistor having a control terminal coupled to a first conductor of the pair of conductors of the corresponding write data line, a first output terminal coupled to the node, and a second output terminal coupled to a first voltage node; a second transistor having a control terminal coupled to a second conductor of the pair of conductor of the corresponding write data line, a first output terminal coupled to the node, and a second output terminal coupled to a second voltage node; and a second switch adapted to couple the output of the bistable latch to the corresponding bit line when the corresponding read select line is enabled.
17. The memory of claim 16 , wherein the bistable latch comprises cross-coupled inverters, first and second pairs of series-coupled transistors are MOS transistors, the switch is a transmission gate, the first voltage node is a ground node, and the second voltage node is a power supply node.
18. The memory of claim 16 , wherein bistable latch comprises cross-coupled inverters, one of the inverters being weaker than the other, the weaker inverter having an output coupled to the input of the bistable latch.
19. The memory of claim 15 , wherein each memory cell comprises: a bistable latch having an input and an output; a first pair of series-coupled transistors coupled between a first voltage node and the input of the bistable latch, one transistor of the first pair of transistors having a control terminal coupled to a first conductor of the pair of conductors of the corresponding write data line and the other transistor of the first pair of transistors having a control terminal coupled to the corresponding write select line; and a second pair of series-coupled transistors coupled between a second voltage node and the input of the bistable latch, one transistor of the second pair of transistors having a control terminal coupled to a second conductor of the pair of conductors of the corresponding write data line and the other transistor of the second pair of transistors having a control terminal coupled to the corresponding write select line; and a switch adapted to couple the output of the bistable latch to a corresponding bit line when a corresponding read select line is enabled.
20. The memory of claim 19 , wherein the bistable latch comprises cross-coupled inverters, first and second pairs of series-coupled transistors are MOS transistors, the switch is a transmission gate, the first voltage node is a ground node, and the second voltage node is a power supply node.
21. The memory of claim 19 , wherein bistable latch comprises cross-coupled inverters, one of the inverters being weaker than the other, the weaker inverter having an output coupled to the input of the bistable latch.
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July 7, 2008
September 21, 2010
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