Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for operating non-volatile storage, comprising: a) performing programming operations on a first set of storage elements using a first verify level less an offset to distinguish slower and faster programming storage elements, while locking out at least a second set of storage elements from being programmed; b) locking out the faster programming storage elements while continuing programming of the slower programming storage elements using the first verify level and while continuing to lock out the at least a second set of storage elements; c) locking out the slower programming storage elements while resuming programming of the faster programming storage elements using the first verify level and while programming the at least a second set of storage elements using at least a second verify level which is less than the first verify level less the offset.
2. The method of claim 1 , further comprising: the first set of storage elements and the at least a second set of storage elements are programmed from a common threshold voltage distribution.
3. The method of claim 1 , further comprising: performing programming operations on the first and second sets of storage elements prior to step a), including applying program pulses which are incremented by a first step size, step b) includes applying program pulses which are incremented by a higher, second step size.
4. The method of claim 3 , wherein: step a) includes applying a first set of program pulses which are incremented by a first step size, and step b) includes applying a second set of program pulses, a first program pulse of the second set is incremented from a last program pulse of the first set of program pulses by more than the first step size.
5. The method of claim 4 , wherein: the first program pulse of the second set is incremented from the last program pulse of the first set of program pulses by the offset.
6. The method of claim 1 , wherein: the first verify level is for a highest data state, and the at least a second verify level is for a second highest data state.
7. The method of claim 1 , wherein: step c) includes programming a third set of storage elements using a third verify level which is less than the second verify level.
8. The method of claim 1 , wherein: steps a) and b) allow programming only of storage elements which are intended to be programmed to a data state associated with the first verify level.
9. The method of claim 1 , further comprising: concluding step a) when a specified number or portion of storage elements in the first set of storage elements have been verified at the first verify level less the offset.
10. The method of claim 1 , wherein step a) comprises applying program pulses, the method further comprising: concluding step a) when a specified number of the program pulses have been applied.
11. The method of claim 1 , wherein step a) comprises applying program pulses, the method further comprising: concluding step a) when a specified number of additional program pulses have been applied after a specified number or portion of storage elements in the first set of storage elements have been verified at the first verify level less the offset.
12. A method for operating non-volatile storage, comprising: programming a first set of storage elements which are intended to be programmed to a first data state associated with a first verify level, while locking out from programming at least a second set of storage elements which are intended to be programmed to a second data state associated with a second verify level, and a third set of storage elements which are intended to be programmed to a third data state associated with a third verify level, the second and third verify levels are below the first verify level; during the programming, distinguishing slower and faster programming storage elements among the first set of storage elements, and locking out the faster programming storage elements while continuing programming of the slower programming storage elements under a first programming condition; and subsequently programming the at least a second and third sets of storage elements to the second and third data states, respectively, while resuming programming of the faster programming storage elements to the first data state under a second programming condition which differs from the first programming condition.
13. The method of claim 12 , wherein: the first and second programming conditions comprise first and second programming pulse step sizes, respectively.
14. The method of claim 12 , wherein: the first and second programming conditions comprise first and second bit line voltages, respectively.
15. The method of claim 12 , wherein: the first and second programming conditions comprise first and second maximum numbers of program pulses, respectively, in a fine programming mode which follows a coarse programming phase.
16. The method of claim 12 , wherein: the first and second programming conditions comprise first and second channel boosting modes, respectively.
17. A method for operating non-volatile storage, comprising: a) programming a first set of storage elements which are intended to be programmed to a first data state associated with a first verify level, while locking out from programming a second set of storage elements which are intended to be programmed to a second data state associated with a second verify level, and a third set of storage elements which are intended to be programmed to a third data state associated with a third verify level, where the third verify level is below the second verify level and the second verify level is below the first verify level; and b) after step a), programming the second and third sets of storage elements, step a) uses a programming condition which differs from a programming condition of step b), the different programming conditions comprise different boosting modes which are implemented by applying a voltage to unselected word lines in step a) which differs from a voltage applied to unselected word lines in step b).
18. The method of claim 17 , wherein: steps a) and b) each include applying a series of step-wise increasing program pulses, and the different programming conditions include different programming pulse step sizes in steps a) and b).
19. The method of claim 17 , wherein: steps a) and b) each include applying a series of program pulses in a coarse programming phase and a following fine programming mode, and the different programming conditions include bit line voltages raised to a level in the fine programming mode of step a) which differs from a level in the fine programming mode of step b).
20. The method of claim 17 , wherein: steps a) and b) each include applying a series of program pulses in a coarse programming phase and a following fine programming mode, and the different programming conditions include allowing a maximum number of program pulses in the fine programming mode of step a) which differs from a maximum number of program pulses in the fine programming mode of step b).
21. The method of claim 17 , wherein: step b) further includes locking out from programming the first set of storage elements.
22. A method for operating non-volatile storage, comprising: a) programming a first set of storage elements which are intended to be programmed to a first data state associated with a first verify level from an erased state to an intermediate state which is associated with an intermediate verify level, the intermediate verify level is below the first verify level; b) programming a second set of storage elements which are intended to be programmed to a second data state which is associated with a second verify level from the erased state to the intermediate state, the second verify level is below the first verify level and above the intermediate verify level; c) during step a) and b), locking out from programming a third set of storage elements which are intended to be programmed to a third data state which is associated with a third verify level, the third verify level is below the intermediate verify level and above the erased state; and d) using a programming condition which differs from a programming condition used in step a), programming the second set storage elements from the intermediate state to the second data state, and programming the third set storage elements from the erased state to the third data state.
23. A non-volatile storage system which performs the method of claim 1 .
24. A non-volatile storage system which performs the method of claim 12 .
25. A non-volatile storage system which performs the method of claim 17 .
26. A non-volatile storage system which performs the method of claim 22 .
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 27, 2008
September 21, 2010
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