Analog comparison circuits are provided, each of which compares the potentials of the same stage of a first boosting cell row and a second boosting cell row and selecting and outputting the lower potential. The P-well potentials of switching devices having a triple-well structure are controlled using the output potentials of these analog comparison circuits. As a result, the amplitude of the P-well potential can be suppressed and a common P-well region can be arranged.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A booster circuit comprising: boosting cells each having a first-conductivity type first well region on a substrate, a second-conductivity type second well region in the first well region, and at least one first switching element in either or both of the first well region and the second well region; a first boosting cell row including N stages (N≧1) of the boosting cells; a second boosting cell row including M stages (M≧1) of the boosting cells; and a first analog comparison circuit for outputting one having the larger absolute value of voltages of an output potential of the boosting cell in the i-th stage (1≦i≦N) of the first boosting cell row and an output potential of the boosting cell in the i-th stage (1≦i≦M) of the second boosting cell row, wherein an output potential of the first analog comparison circuit is applied to the second well region of the at least one first switching element included in at least one of the boosting cells in a k-th stage (1≦k≦i).
2. The booster circuit of claim 1 , further comprising: a backflow preventing circuit having a first-conductivity type third well region on the substrate, a second-conductivity type fourth well region in the third well region, and at least one second switching element in either or both of the third well region and the fourth well region, wherein the backflow preventing circuit is further provided in the first boosting cell row to form a third boosting cell row, the backflow preventing circuit is further provided in the second boosting cell row to form a fourth boosting cell row, and the output potential of the first analog comparison circuit provided in the boosting cell in the i-th stage (1≦i≦N and 1≦i≦M) is applied to the fourth well region of the at least one second switching device provided in at least one of the backflow preventing circuits.
3. The booster circuit of claim 1 , further comprising: a backflow preventing circuit having a first-conductivity type third well region on the substrate, a second-conductivity type fourth well region in the third well region, and at least one second switching element in either or both of the third well region and the fourth well region, a third boosting cell row formed by further providing the backflow preventing circuit in the first boosting cell row; a fourth boosting cell row formed by further providing the backflow preventing circuit in the second boosting cell row; and a second analog comparison circuit for comparing a first internal node voltage of the backflow preventing circuit provided in the third boosting cell row and a second internal node voltage of the backflow preventing circuit provided in the fourth boosting cell row, wherein an output potential of the second analog comparison circuit is applied to the fourth well region of the at least one second switching device provided in at least one of the backflow preventing circuits.
4. The booster circuit of claim 1 , wherein the first analog comparison circuit is provided for each of all the boosting cell stages.
5. The booster circuit of claim 1 , wherein the first analog comparison circuit is provided every arbitrary number of boosting cells.
6. The booster circuit of claim 1 , wherein the first analog comparison circuit has a first-conductivity type fifth well region on the substrate, a second-conductivity type sixth well region in the fifth well region, and at least one third switching device in the sixth well region.
7. The booster circuit of claim 3 , wherein the second analog comparison circuit has a first-conductivity type seventh well region on the substrate, a second-conductivity type eighth well region in the seventh well region, and at least one fourth switching device in the eighth well region.
8. The booster circuit of claim 6 , wherein the second well region of the at least one first switching device and the sixth well region of the at least one third switching device are a common well region shared by the at least one first switching device and the at least one third switching device.
9. The booster circuit of claim 7 , the fourth well region of the at least one second switching device and the eighth well region of the at least one fourth switching device are a common well region shared by the at least one second switching device and the at least one fourth switching device.
10. A booster circuit comprising: boosting cells each having a first-conductivity type first well region on a substrate, a second-conductivity type second well region in the first well region, and at least one first switching element in either or both of the first well region and the second well region; a first boosting cell row including N stages (N≧1) of the boosting cells; a second boosting cell row including M stages (M≧1) of the boosting cells; and a first analog comparison circuit for outputting one having the larger absolute value of voltages of an output potential of the boosting cell in the i-th stage (1≦i≦N) of the first boosting cell row and an output potential of the boosting cell in the i-th stage of the second boosting cell row, wherein the second well region of the boosting cell in the i-th stage (1≦i≦N) of the first boosting cell row and the second well region of the boosting cell in the i-th stage (1≦i≦M) of the second boosting cell row are a common well region shared by the boosting cell in the i-th stage (1≦i≦N) of the first boosting cell row and the boosting cell in the i-th stage (1≦i≦M) of the second boosting cell row.
11. The booster circuit of claim 10 , further comprising: a backflow preventing circuit having a first-conductivity type third well region on the substrate, a second-conductivity type fourth well region in the third well region, and at least one second switching element in either or both of the third well region and the fourth well region, wherein the backflow preventing circuit is further provided in the first boosting cell row to form a third boosting cell row, the backflow preventing circuit is further provided in the second boosting cell row to form a fourth boosting cell row, and the fourth well region of the backflow preventing circuit provided in the third boosting cell row and the fourth well region of the backflow preventing circuit provided in the fourth boosting cell row are a common well region shared by the backflow preventing circuit provided in the third boosting cell row and the backflow preventing circuit provided in the fourth boosting cell row.
12. The booster circuit of claim 6 , wherein an output voltage of the first analog comparison circuit is applied to the sixth well region of the first analog comparison circuit.
13. The booster circuit of claim 7 , wherein an output voltage of the second analog comparison circuit is applied to the eighth well region of the second analog comparison circuit.
14. The booster circuit of claim 10 , wherein an output voltage of the first analog comparison circuit is applied to a third well region of the first analog comparison circuit.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 24, 2009
October 5, 2010
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