Analog memory

1. An analog memory, comprising: a plurality of memory blocks for charging and discharging electric charges corresponding to an input signal, each of the plurality of memory blocks including a plurality of switched capacitor portions each having a capacitive element, a first switching element with an input terminal and a second switching element with an output terminal; a charge line commonly connected to the input terminals of the plurality of the switched capacitor portions of the plurality of memory blocks; a plurality of discharge lines each commonly connected to the output terminals of the switched capacitor portions in each of the plurality of memory blocks; and a buffer circuit disconnectably connected to each of the plurality of memory blocks via the corresponding discharge line and configured to output an output signal, wherein the plurality of memory blocks are configured to sequentially discharge the electric charges to the buffer circuit via the corresponding discharge line, and wherein discharging of one of the plurality of memory blocks is performed in a state in which a subsequent memory block supposed to perform the subsequent discharging is connected to the buffer circuit with the remaining memory blocks disconnected from the butter circuit.

2. The analog memory as recited in claim 1 , wherein the first switching element is a MOS transistor and the second switching element is a MOS transistor.

3. The analog memory as recited in claim 1 , wherein the one of the plurality of memory blocks and the subsequent memory block are connected to the buffer circuit via the corresponding discharge lines with the remaining memory blocks disconnected from the butter circuit at least during a time period in which a last stage switched capacitor portion in the one of the memory blocks performs charging and a first stage switched capacitor portion in the subsequent memory block performs discharging.

4. The analog memory as recited in claim 1 , wherein each of the plurality of switched capacitor portions comprises a first MOS transistor as the first switching element functioning as a charging switch, a second MOS transistor as the second switching element functioning as a discharging switch, and a capacitive element for charging the electric charges, and wherein each of the plurality of switched capacitor portions is configured such that one end of the capacitive element is commonly connected to a source of the first MOS transistor and a source of the second MOS transistor with the other end grounded and the charge line is connected to a drain of the first MOS transistor and the discharge lines is connected to a drain of the second MOS transistor.

5. The analog memory as recited in claim 1 , wherein connection of the plurality of memory blocks to the buffer circuit is controlled by operating line selection switches provided in each of the plurality of the discharge lines.

6. The analog memory as recited in claim 1 , wherein the buffer circuit comprises an operational amplifier having an inverting input terminal and an output terminal in which the inverting input terminal and the output terminal are connected in a negative feedback arrangement.

7. An analog memory, comprising a first to third memory blocks, wherein each of the first to third memory blocks includes: a plurality of capacitive elements for storing electric charges corresponding to an input signal; an output line for transferring the electric charges; and a plurality of MOS transistors each for changing connection between the capacitive element and the output line, wherein, when a signal is outputted from the first memory block to a buffer circuit via the output line of the first memory block by sequentially connecting the capacitive element in the first memory block to the output line thereof, the capacitive elements and the output line in the second and third memory blocks are disconnected with the first memory block and the second memory block connected to the buffer circuit via the output lines of the first and second memory blocks.

8. The analog memory as recited in claim 7 , wherein the output line of the first memory block and the output line of the third memory block are disconnected.

9. The analog memory as recited in claim 7 , wherein the input signal is impressed to the first to third memory blocks via a common input line.

10. The analog memory as recited in claim 7 , wherein the buffer circuit comprises an operational amplifier having an inverting input terminal and an output terminal in which the inverting input terminal and the output terminal are connected in a negative feedback arrangement.

11. The analog memory as recited in claim 1 , further comprising a plurality of line selection switches each provided between each of the plurality of the memory blocks and the butter circuit.

12. The analog memory as recited in claim 7 , further comprising a plurality of line selection switches each provided between each of the plurality of memory blocks and the butter circuit.