A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; an epitaxial region having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the epitaxial region comprises an impurity of a first conductivity type; a first portion of the semiconductor substrate adjoining the epitaxial region, wherein the first portion of the semiconductor substrate is of the first conductivity type; and a second portion of the semiconductor substrate adjoining the first portion. The second portion of the semiconductor substrate is of a second conductivity type opposite the first conductivity type. A silicide region is formed on the epitaxial region and the first and the second portions of the semiconductor substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor structure comprising: a semiconductor substrate; a gate stack of an MOS device on the semiconductor substrate; an epitaxial region having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the epitaxial region comprises an impurity of a first conductivity type; a first portion of the semiconductor substrate adjoining the epitaxial region, wherein the first portion of the semiconductor substrate is of the first conductivity type, and wherein the epitaxial region and the first portion of the semiconductor substrate have an interface extending in a direction parallel to a gate length direction of the MOS device; a second portion of the semiconductor substrate adjoining the first portion, wherein the second portion of the semiconductor substrate is of a second conductivity type opposite the first conductivity type; and a silicide region on the epitaxial region and the first and the second portions of the semiconductor substrate.
2. The semiconductor structure of claim 1 , wherein the epitaxial region comprises silicon germanium, and wherein the first portion is of p-type, and the second portion is of n-type.
3. The semiconductor structure of claim 1 , wherein the first portion is of n-type, and the second portion is of p-type.
4. The semiconductor structure of claim 1 further comprising a contact connected to a portion of the silicide region directly on the second portion of the semiconductor substrate.
5. The semiconductor structure of claim 1 , wherein the first portion of the semiconductor substrate is farther away from the gate stack than the epitaxial region.
6. The semiconductor structure of claim 1 , wherein the MOS device is a first PMOS device, and wherein the second portion of the semiconductor substrate is a pickup region with a contact formed directly over the pickup region.
7. The semiconductor structure of claim 6 further comprising a second PMOS device sharing the epitaxial region as a common source region with the first PMOS device, wherein the gate length direction of the first PMOS device is parallel to a gate length direction of the second PMOS device.
8. The semiconductor structure of claim 1 , wherein the first portion of the semiconductor substrate has a width smaller than a width of the epitaxial region and a width of the second portion of the semiconductor substrate, with the width of the first portion, the width of the epitaxial region, and the width of the second portion being measured in directions parallel to the gate length direction of the MOS device.
9. The semiconductor structure of claim 8 , wherein the width of the first portion of the semiconductor substrate is less than about 0.1 μm.
10. The semiconductor structure of claim 8 , wherein each of the second portion of the semiconductor substrate and the epitaxial region further comprises an additional portion adjoining the first portion of semiconductor substrate, and having a width substantially equal to the width of the first portion of the semiconductor substrate, and wherein the width of the additional portion of the second portion and the additional portion of the epitaxy region are measured in a direction parallel to the gate length direction of the MOS device.
11. A semiconductor structure comprising: a semiconductor substrate; a gate over the semiconductor substrate; a silicon germanium (SiGe) region in the semiconductor substrate, wherein the SiGe region comprises a first portion adjacent the gate and a second portion adjoining the first portion, and wherein the second portion has a width substantially smaller than a width of the first portion; a heavily doped p-type region adjoining the second portion of the SiGe region, wherein the heavily doped p-type region has a substantially same width as the second portion of the SiGe region; and a pickup region adjoining the heavily doped p-type region, wherein the pickup region is of n-type, and comprises an extension adjoining the heavily doped p-type region, and wherein the extension of the pickup region and the second portion of the SiGe region have a substantially same width.
12. The semiconductor structure of claim 11 further comprising a silicide region on the SiGe region, the heavily doped p-type region and the pickup region.
13. The semiconductor structure of claim 11 , wherein the second portion of the SiGe region has a length of greater than about 0.1 μm.
14. The semiconductor structure of claim 11 , wherein the second portion of the SiGe region has a width of less than about 0.08 μm.
15. The semiconductor structure of claim 11 further comprising a shallow trench isolation region on an opposite side of the first portion of the SiGe region than the gate, wherein the shallow trench isolation region contacts the first portion of the SiGe region.
16. The semiconductor structure of claim 11 further comprising an additional gate over the semiconductor substrate, wherein the additional gate is on an opposite side of the first portion of the SiGe region than the gate.
17. The semiconductor structure of claim 11 , wherein the gate is a portion of a PMOS device, and wherein an interface between the extension of the pickup region and the heavily doped p-type region is parallel to a gate length direction of the PMOS device.
18. A semiconductor structure comprising: a semiconductor substrate; a first p-type metal-oxide-semiconductor (PMOS) device comprising a first gate polysilicon on the semiconductor substrate; a second PMOS device comprising a second gate polysilicon on the semiconductor substrate, wherein the first and the second gate polysilicons are parallel to a first direction; a SiGe region between and adjacent the first and the second gate polysilicons, the SiGe region having a first width measured in a second direction perpendicular to the first direction; a SiGe extension adjoining the SiGe region; a P+ region adjoining the SiGe extension, wherein the P+ region and the SiGe extension have a first interface substantially parallel to the second direction; an N+ extension region adjoining the P+ region, wherein the SiGe extension, the P+ region, and the N+ extension region have a same second width smaller than the first width and measured in a direction parallel to the second direction; and a pickup region adjoining the N+ extension region, wherein the pickup region is an N+ region.
19. The semiconductor structure of claim 18 further comprising: a silicide region on the SiGe extension, the P+ region, the N+ extension region, and the pickup region; a contact physically contacting the silicide region, wherein the contact is directly over the pickup region.
20. The semiconductor structure of claim 18 , wherein the P+ region and the N+ extension region have a second interface substantially parallel to the second direction.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 12, 2007
October 19, 2010
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