A shift register for use in an LCD is disclosed. The shift register provides better gate driving signals with the lower coupling effect. The shift register includes two switches. The control node of the first switch is electrically coupled to the control node of the second switch. One end of the first switch receives a clock signal, and the other end of the first switch is electrically coupled to one end of the second switch. The other end of the second switch outputs a gate driving signal. Both of the two switches are controlled by a control signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A shift register with lower coupling effect comprising: a first switch comprising: a first end; a second end; and a control end electrically coupled to the first end of the first switch; an output end; a first control circuit comprising: a first input end for receiving a first clock signal; a second input end for receiving a second clock signal; a third input end electrically coupled to the first end of the first switch; a first output end electrically coupled to the second end of the first switch; and a second output end electrically coupled to the output end of the shift register; a second control circuit comprising: a first input end for receiving the second clock signal; a second input end electrically coupled to the first end of the first switch; a first output end electrically coupled to the second end of the first switch; and a second output end electrically coupled to the output end of the shift register; a third control circuit comprising: an input end; a first output end electrically coupled to the second end of the first switch; and a second output end electrically coupled to the output end of the shift register; a second switch comprising: a first end for receiving the first clock signal; a second end; and a control end electrically coupled to the second end of the first switch; and a third switch comprising: a first node electrically coupled to the second end of the second switch; a second end electrically coupled to the output end of the shift register; and a control node electrically coupled to the second end of the first switch.
2. The shift register of claim 1 , wherein the first, the second, and the third switches are thin film transistors, and the control ends of the first, second, and third switches are the gates of the thin film transistors.
3. The shift register of claim 1 , wherein the phase difference of the first clock signal and the second clock signal is 180 degrees.
4. The shift register of claim 1 , wherein the first control circuit further comprises: a first switch comprising: a first end; a second end; and a control end electrically coupled to the third input end of the first control circuit; a second switch comprising: a first end electrically coupled to the first end of the first switch; and a second end electrically coupled to the second input end of the first control circuit; a third switch comprising: a first end electrically coupled to the first input end of the first control circuit; a second end electrically coupled to the first end of the first switch; and a control end electrically coupled to the first input end of the first control circuit; a fourth switch comprising: a first end electrically coupled to the first output end of the first control circuit; a second end electrically coupled to the second end of the first switch; and a control end electrically coupled to the first end of the first switch; a fifth switch comprising: a first end electrically coupled to the second output end of the first control circuit; a second end electrically coupled to the second end of the first switch; and a control end electrically coupled to the first end of the first switch; and a six switch comprising: a first end electrically coupled to the first end of the first switch; a second end electrically coupled to the second end of the first switch; and a control end electrically coupled to the second output end of the first control circuit.
5. The shift register of claim 4 , wherein the first, second, third, fourth, fifth, and sixth switches are thin film transistors, and the control ends of the first, second, third, fourth, fifth, and sixth switches are the gates of the thin film transistors.
6. The shift register of claim 1 wherein the second control circuit further comprises: a first switch comprising: a first end electrically coupled to the first output end of the second control circuit; a second end electrically coupled to the second input end of the second control circuit; and a control end electrically coupled to the first input end of the second control circuit; and a second switch comprising: a first end electrically coupled to the second output end of the second control circuit; a second end; and a control end electrically coupled to the first input end of the second control circuit.
7. The shift register of claim 6 wherein the first and the second switches are thin film transistors, and the control ends of the first and the second switches are the gates of the thin film transistors.
8. The shift register of claim 1 wherein the third control circuit further comprises: a first switch comprising: a first end electrically coupled to the first output end of the third control circuit; a second end; and a control end electrically coupled to the input end of the third control circuit; and a second switch comprising: a first end electrically coupled to the second output end of the third control circuit; a second end electrically coupled to the second end of the first switch; and a control end electrically coupled to the input end of the third control circuit.
9. The shift register of claim 8 wherein the first and the second switches are thin film transistors, and the control ends of the first and the second switches are the gates of the thin film transistors.
10. A liquid crystal display with lower coupling effect comprising: a first glass substrate comprising: a plurality of cascade-connected shift registers, each shift register with lower coupling effect comprising: a first switch comprising: a first end; a second end; and a control end electrically coupled to the first end of the first switch; an output end; a first control circuit comprising: a first input end for receiving a first clock signal; a second input end for receiving a second clock signal; a third input end electrically coupled to the first end of the first switch; a first output end electrically coupled to the second end of the first switch; and a second output end electrically coupled to the output end of the shift register; a second control circuit comprising: a first input end for receiving the second clock signal; a second input end electrically coupled to the first end of the first switch; a first output end electrically coupled to the second end of the first switch; and a second output end electrically coupled to the output end of the shift register; a third control circuit comprising: an input end; a first output end electrically coupled to the second end of the first switch; and a second output end electrically coupled to the output end of the shift register; a second switch comprising: a first end for receiving the first clock signal; a second end; and a control end electrically coupled to the second end of the first switch; and a third switch comprising: a first node electrically coupled to the second end of the second switch; a second end electrically coupled to the output end of the shift register; and a control node electrically coupled to the second end of the first switch; and a pixel circuit electrically coupled to at least an output end of one shift register of the plurality of the cascade-connected shift registers; a second glass substrate; and a liquid crystal layer formed between the first glass substrate and the second glass substrate.
11. The liquid crystal display of claim 10 wherein the first, the second, and the third switches are thin film transistors, and the control ends of the first, second, and third switches are the gates of the thin film transistors.
12. The liquid crystal display of claim 10 wherein the phase difference of the first clock signal and the second clock signal is 180 degrees.
13. The liquid crystal display of claim 10 wherein the first control circuit further comprises: a first switch comprising: a first end; a second end; and a control end electrically coupled to the third input end of the first control circuit; a second switch comprising: a first end electrically coupled to the first end of the first switch; and a second end electrically coupled to the second input end of the first control circuit; a third switch comprising: a first end electrically coupled to the first input end of the first control circuit; a second end electrically coupled to the first end of the first switch; and a control end electrically coupled to the first input end of the first control circuit; a fourth switch comprising: a first end electrically coupled to the first output end of the first control circuit; a second end electrically coupled to the second end of the first switch; and a control end electrically coupled to the first end of the first switch; a fifth switch comprising: a first end electrically coupled to the second output end of the first control circuit; a second end electrically coupled to the second end of the first switch; and a control end electrically coupled to the first end of the first switch; and a six switch comprising: a first end electrically coupled to the first end of the first switch; a second end electrically coupled to the second end of the first switch; and a control end electrically coupled to the second output end of the first control circuit.
14. The liquid crystal display of claim 13 , wherein the first, second, third, fourth, fifth, and sixth switches are thin film transistors, and the control ends of the first, second, third, fourth, fifth, and sixth switches are the gates of the thin film transistors.
15. The liquid crystal display of claim 10 wherein the second control circuit further comprises: a first switch comprising: a first end electrically coupled to the first output end of the second control circuit; a second end electrically coupled to the second input end of the second control circuit; and a control end electrically coupled to the first input end of the second control circuit; and a second switch comprising: a first end electrically coupled to the second output end of the second control circuit; a second end; and a control end electrically coupled to the first input end of the second control circuit.
16. The shift liquid crystal display of claim 15 wherein the first and the second switches are thin film transistors, and the control ends of the first and the second switches are the gates of the thin film transistors.
17. The liquid crystal display of claim 10 wherein the third control circuit further comprises: a first switch comprising: a first end electrically coupled to the first output end of the third control circuit; a second end; and a control end electrically coupled to the input end of the third control circuit; and a second switch comprising: a first end electrically coupled to the second output end of the third control circuit; a second end electrically coupled to the second end of the first switch; and a control end electrically coupled to the input end of the third control circuit.
18. The shift register of claim 17 wherein the first and the second switches are thin film transistors, and the control ends of the first and the second switches are the gates of the thin film transistors.
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March 15, 2007
October 19, 2010
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