Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N+ doped source region is disposed in the NDD region. An N+ doped region is disposed in the first P-body region. A P+ doped region is disposed in the second P-body region. A first gate is disposed between the N+ doped region and the isolation region, and a second gate is disposed between the N+ doped region and the P+ doped region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A trig modulation electrostatic discharge (ESD) protection device, comprising: a semiconductor substrate; a first transistor having a first drain electrically coupled to a first voltage, a first source electrically coupled to a second voltage, a first gate electrically coupled to a first end of a capacitor and a second of a resistor; and a second transistor having a second drain electrically coupled to a body of the first transistor, a second source electrically coupled to the second voltage and a first end of the resistor, and a second gate electrically coupled to the first gate of the first transistor, wherein a body of the second transistor is electrically coupled to the first voltage and a second end of the capacitor, wherein the second transistor includes a depleted PMOS transistor.
2. The trig modulation electrostatic discharge (ESD) protection device as claimed in claim 1 , wherein the first voltage is a driving voltage, and the second voltage is grounded.
3. The trig modulation electrostatic discharge (ESD) protection device as claimed in claim 1 , wherein the first transistor includes an NMOS transistor.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 5, 2008
October 26, 2010
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