A head IC adjusts an amplitude level of a read signal of a head to adjust dispersion of the output characteristic of the head and to adjust the read signal within the input dynamic range of the AGC of a read channel. An AGC amplifier is installed in a head IC connected to a read channel and a feedback response speed of an AGC circuit of the head IC is set to be sufficiently slower than a feedback response speed of an AGC circuit of the read channel. Also a peak hold circuit and an amplitude limiting circuit are installed in the head IC, and gain is adjusted with a holding value of the peak hold circuit. An initial gain can therefore be stably adjusted at high-speed without being influenced by signals having a small amplitude on the medium.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A head IC for adjusting an amplitude level of a read signal from a head which reads a signal from a recording medium, and outputting the adjusted read signal to a read channel which has an AGC amplifier, comprising: a differential amplifier for amplifying said read signal with a gain being set; an envelope circuit for detecting an output amplitude level of said differential amplifier; a gain error computing unit for computing a difference between said detected output amplitude level and a reference level; a feedback circuit which has a pull-in characteristic that is slower than a pull-in characteristic of the AGC amplifier of said read channel, and for automatically controlling a gain of said differential amplifier according to a gain error amount which is said difference; a peak hold circuit for holding a maximum value of said output amplitude level; and an amplitude limiting circuit for cutting an input of said output amplitude level which is smaller than said holding value of said peak hold circuit to said gain error computing unit according to said holding value, when said gain is initialized.
2. The head IC according to claim 1 , wherein said amplitude limiting circuit comprises a switch for inputting said holding value of said peak hold circuit to said gain error computing unit when said gain is initialized, and for inputting said detected output amplitude level of said envelope circuit to said gain error computing unit after said gain initialization is over.
3. The head IC according to claim 1 , further comprising: a comparison circuit for comparing a 1/N (N>1) value of said holding value of said peak hold circuit and said detected output amplitude level of said envelope circuit when said gain is initialized, wherein said amplitude limiting circuit comprises a switch for inputting said output amplitude level to said gain error computing unit if said output amplitude level is greater than said 1/N value.
4. The head IC according to claim 1 , further comprises: a memory for storing an initial value of said adjusted gain; and a sequence circuit for setting an initial value of a gain of said memory in said differential amplifier when pull-in starts.
5. The head IC according to claim 4 , further comprising a head switching section for connecting one of a plurality of heads to said differential amplifier according to a head select signal, wherein said memory stores initial values of gains of said plurality of heads, and said sequence circuit sets the initial value of the gain corresponding to said connected head of said memory in said differential amplifier when said pull-in starts.
6. The head IC according to claim 1 , further comprising a sequence circuit for setting a pull-in characteristic of said feedback circuit to be fast, and instructing a gain of the AGC amplifier of said read channel to a fixed gain at said start up, and setting the pull-in characteristic of said feedback circuit to a characteristic slower than the pull-in characteristic of the AGC amplifier of said read channel when said pull-in ends.
7. The head IC according to claim 1 , wherein said feedback circuit comprises: a low pass filter for cutting the high frequency component of the output of said difference from said gain error computing unit; and a gain multiplier for multiplying an output of said low pass filter by a predetermined feedback gain, and controlling the gain of said differential amplifier.
8. A read circuit for adjusting an amplitude level of a read signal from a head which reads a signal from a medium, comprising: a head IC for adjusting an amplitude level of a read signal from said head; and a read channel which is connected to said head IC and has an AGC amplifier, wherein said head IC comprises: a differential amplifier for amplifying said read signal with a gain being set; an envelope circuit for detecting an output amplitude level of said differential amplifier; a gain error computing unit for computing a difference between said detected output amplitude level and a reference level; a feedback circuit which has a pull-in characteristic that is slower than a pull-in characteristic of the AGC amplifier of said read channel, and for automatically controlling a gain of said differential amplifier according to a gain error amount which is said difference; a peak hold circuit for holding a maximum value of said output amplitude level; and an amplitude limiting circuit for cutting an input of said output amplitude level which is smaller than said holding value of said peak hold circuit to said gain error computing unit according to said holding value, when said gain is initialized.
9. The read circuit according to claim 8 , wherein said amplitude limiting circuit comprises a switch for inputting said holding value of said peak hold circuit to said gain error computing unit when said gain is initialized, and for inputting said detected output amplitude level of said envelope circuit to said gain error computing unit after said gain initialization is over.
10. The read circuit according to claim 8 , further comprising: a comparison circuit for comparing a 1/N (N>1) value of said holding value of said peak hold circuit and said detected output amplitude level of said envelope circuit when said gain is initialized, wherein said amplitude limiting circuit comprises a switch for inputting said output amplitude level to said gain error computing unit if said output amplitude level is greater than said 1/N value.
11. The read circuit according to claim 8 , wherein said head IC further comprises: a memory for storing an initial value of said adjusted gain; and a sequence circuit for setting an initial value of a gain of said memory to said differential amplifier when pull-in starts.
12. The read circuit according to claim 11 , further comprising a head switching section for connecting one of a plurality of heads to said differential amplifier according to a head select signal, wherein said memory stores initial values of gains of said plurality of heads, and said sequence circuit sets the initial value of the gain corresponding to said connected head of said memory in said differential amplifier when said pull-in starts.
13. The read circuit according to claim 8 , further comprising a sequence circuit for setting a pull-in characteristic of said feedback circuit to be fast, and instructing a gain of the AGC amplifier of said read channel to a fixed gain at said start up, and setting the pull-in characteristic of said feedback circuit to a characteristic slower than the pull-in characteristic of the AGC amplifier of said read channel when said pull-in ends.
14. The read circuit according to claim 8 , wherein said feedback circuit comprises: a low pass filter for cutting a high frequency component of the output of said difference from said gain error computing unit; and a gain multiplexer for multiplying the output of said low pass filter by a predetermined feedback gain, and controlling the gain of said differential amplifier.
15. A medium storage device, comprising: a head for reading a medium; a head IC for adjusting an amplitude level of a read signal from said head; and a read channel which is connected to said IC and has an AGC amplifier, wherein said head IC comprises: a differential amplifier for amplifying said read signal with a gain being set; an envelope circuit for detecting an output amplitude level of said differential amplifier; a gain error computing unit for computing a difference between said detected output amplitude level and a reference level; a feedback circuit which has a pull-in characteristic that is slower than a pull-in characteristic of the AGC amplifier of said read channel, and automatically controls a gain of said differential amplifier according to a gain error amount which is said difference; a peak hold circuit for holding a maximum value of said output amplitude level; and an amplitude limiting circuit for cutting an input of said output amplitude level which is smaller than said holding value of said peak hold circuit to said gain error computing unit according to said holding value, when said gain is initialized.
16. The medium storage device according to claim 15 , wherein said amplitude limiting circuit comprises a switch for inputting said holding value of said peak hold circuit to said gain error computing unit when said gain is initialized, and inputting said detected output amplitude level of said envelope circuit to said gain error computing unit after said gain initialization is over.
17. The medium storage device according to claim 15 , further comprising: a comparison circuit for comparing a 1/N (N>1) value of said holding value of said peak hold circuit and said detected output amplitude level of said envelope circuit when said gain is initialized, wherein said amplitude limiting circuit comprises a switch for inputting said output amplitude level to said gain error computing unit if said output amplitude level is greater than said 1/N value.
18. The medium storage device according to claim 15 , wherein said head IC further comprises: a memory for storing an initial value of said adjusted gain; and a sequence circuit for setting an initial value of a gain of said memory to said differential amplifier when pull-in starts.
19. The medium storage device according to claim 18 , further comprising a head switching section for connecting one of a plurality of heads to said differential amplifier according to a head select signal, wherein said memory stores initial values of gains of said plurality of heads, and said sequence circuit sets the initial value of the gain corresponding to said connected head of said memory in said differential amplifier when said pull-in starts.
20. The medium storage device according to claim 15 , further comprising a sequence circuit for setting a pull-in characteristic of said feedback circuit to be fast, and instructing a gain of the AGC amplifier of said read channel to a fixed gain at said start up, and setting the pull-in characteristic of said feedback circuit to a characteristic slower than the pull-in characteristic of the AGC amplifier of said read channel when said pull-in ends.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 28, 2007
October 26, 2010
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