In one embodiment of the disclosure, a method includes providing a carrier substrate, forming a first region over an upper surface of the substrate, creating an electrical component using a planar process, embedding the electrical component in the dielectric layer, and removing a substrate portion of the electrical component. The first region includes a dielectric layer and may be made of any material that electrically isolates the electrical component from the carrier substrate. The electrical component may be created using a planar process thereby having an epitaxial surface that is embedded in the dielectric layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for manufacturing a multiple substrate electrical circuit device comprising: providing an integrated circuit having an upper surface; forming a conductive layer over the upper surface of the integrated circuit; forming a dielectric layer made of liquid crystal polymer over an upper surface of the conductive layer, the dielectric layer forming an upper dielectric surface; creating, using a planar process, an electrical component having an epitaxial surface and a substrate portion, the electrical component being made from a material that is different than a material from which the integrated circuit is made; embedding the epitaxial surface of the electrical component in the upper dielectric surface; removing the substrate portion from the electrical component; forming an electrical connection between the electrical circuit and the integrated circuit using at least one microstrip line; and forming a thermal bar on the electrical component.
2. The method of claim 1 , wherein creating an electrical component further comprises creating a plurality of electrical components on a wafer and separating each of the electrical components from one another.
3. A method for manufacturing a multiple substrate electrical circuit device comprising: providing a carrier substrate having an upper surface; forming a first region over the upper surface, the first region comprising a dielectric layer having an upper dielectric surface; creating, using a planar process, an electrical component having an epitaxial surface and a substrate portion; embedding the epitaxial surface of the electrical component in the upper dielectric surface; and removing the substrate portion from the electrical component.
4. The method of claim 3 , wherein the first region further comprises a conductive layer disposed in between the upper surface and the dielectric layer.
5. The method of claim 4 , wherein the first region further comprises a second dielectric layer disposed in between the upper surface and the conductive layer.
6. The method of claim 3 , wherein providing a carrier substrate further comprises providing an integrated circuit having an upper surface.
7. The method of claim 3 , further comprising forming an electrical connection between the electrical circuit and the integrated circuit using at least one microstrip line.
8. The method of claim 3 , further comprising forming a thermal bar on the electrical component.
9. The method of claim 3 , wherein applying a dielectric layer over the upper surface comprises applying a dielectric layer made of liquid crystal polymer over the upper surface.
10. The method of claim 3 , wherein creating an electrical component further comprises creating an electrical component from a material that is different than the material from which the carrier substrate is made.
11. The method of claim 3 , wherein creating an electrical component further comprises creating a plurality of electrical components on a wafer and separating each of the electrical components from one another.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 27, 2007
November 2, 2010
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