Patentable/Patents/US-7825621
US-7825621

Junction temperature reduction for three phase inverters modules

PublishedNovember 2, 2010
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

Provided is a motor controller and method of controlling a motor with an improved maximum junction temperature rating. In accordance with one aspect of the present invention, a motor is controlled by varying a common mode voltage duty ratio for a plurality of solid state switching devices in a power inverter, generating drive signals for the solid state switching devices based at least in part upon the common mode voltage duty ratio, and changing states of the solid state switching devices based upon the drive signals.

Patent Claims
25 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method of controlling a motor, comprising: varying a common mode voltage duty ratio for a plurality of solid state switching devices in a power inverter, such that the temperature differences between the solid state switching devices for multiple phases of power are reduced; generating drive signals for the solid state switching devices based at least in part upon the common mode voltage duty ratio; and changing states of the solid state switching devices based upon the drive signals.

2

2. The method of claim 1 , comprising determining a phase angle of output power from the solid state switching devices, and varying the common mode voltage duty ratio based upon the phase angle.

3

3. The method of claim 2 , wherein the phase angle is a current phase angle for one phase of three phase output from the inverter.

4

4. The method of claim 2 , wherein the common mode voltage duty ratio is varied based upon a predetermined duty ratio schedule depending on the phase angle.

5

5. The method of claim 4 , wherein the predetermined duty ratio schedule is computed based upon a comparison of duty ratios to determine a common mode voltage duty ratio that minimizes temperature differences between solid state switching devices for multiple phases of power.

6

6. The method of claim 5 , wherein the predetermined duty ratio schedule is computed based upon a comparison of duty ratios to determine a common mode voltage duty ratio that minimizes temperature differences between solid state switching devices and associated diodes.

7

7. The method of claim 1 , comprising determining an amplitude of an optimal common mode voltage duty ratio and varying the common mode voltage duty ratio as a periodic function with amplitude equal to the amplitude of the optimal common mode voltage duty ratio.

8

8. The method of claim 7 , comprising estimating the optimal common mode voltage duty ratio as a discrete periodic function with an amplitude equal to the maximum magnitude of the optimal common mode voltage duty ratio.

9

9. The method of claim 1 , comprising varying the common mode voltage duty ratio by determining a first possible common mode voltage duty ratio which minimizes the temperature differences between a solid state switching device and a diode of a first leg carrying a maximum phase current, a second possible common mode voltage duty ratio which equates the temperature difference between the solid state switching device and the diode of the first leg and the temperature difference between both the solid state switching device and the diode of the first leg and a solid state switching device of another leg, and a third possible common mode voltage duty ratio which equates the temperature difference between the solid state switching device and the diode of the first leg and the temperature difference between both the solid state switching device and the diode of the first leg and a diode of another leg, and choosing the common mode voltage duty ratio to be the second possible common mode voltage duty ratio if the first possible common mode voltage duty ratio is lower, choosing the common mode voltage duty ratio to be the third possible common mode voltage duty ratio if the first possible common mode voltage duty ratio is lower, otherwise choosing the common mode voltage duty ratio to be the first possible common mode voltage duty ratio.

10

10. The method of claim 1 , wherein the common mode voltage duty ratio is varied only when the output power has a frequency below approximately 5 Hz.

11

11. A motor controller comprising: an inverter including a plurality of solid state switching devices and associated flyback diodes, the switching devices and diodes being interconnected to form a three phase inverter; and control circuitry coupled to the inverter and configured to vary a common mode voltage duty ratio for switching the solid state switching devices, and to generate drive signals for the solid state switching devices based upon the common mode duty ratio, and wherein the control circuitry is configured to vary the common mode voltage duty ratio such that the temperature differences between the solid state switching devices for multiple phases of power are reduced.

12

12. The motor controller of claim 11 , wherein the control circuitry is configured to vary the common mode voltage duty ratio such that the temperature differences between solid state switching devices and associated flyback diodes of at least one phase of power are reduced.

13

13. The motor controller of claim 11 , wherein the control circuitry is configured to determine the phase angle of the output power and to vary the common mode voltage duty ratio as a function of the phase angle.

14

14. The motor controller of claim 13 , wherein the control circuitry is configured to determine an optimal common mode voltage duty ratio amplitude (d m ).

15

15. The motor controller of claim 14 , wherein the control circuitry is configured to determine the optimal common mode voltage duty ratio amplitude (d m ) according to the following equation: d m =d cm (0).

16

16. The motor controller of claim 14 , wherein the control circuitry is configured to vary the common mode voltage duty ratio as a function of phase angle according to the equation: d cm ′(θ i )=d m cos(3·θ i ).

17

17. The motor controller of claim 14 , wherein the control circuitry is configured to vary the common mode voltage duty ratio as a function of phase angle according to the equation: d c ⁢ ⁢ m ″ ⁡ ( θ i + k · 2 ⁢ π 3 ) = { d m - ⁣ π 9 < θ i < π 9 0 π 9 < θ i < 2 ⁢ π 9 - d m 2 ⁢ π 9 < θ i < 4 ⁢ π 9 0 4 ⁢ π 9 < θ i < 5 ⁢ π 9 k = 0 , 1 , … .

18

18. The motor controller of claim 14 , comprising memory circuitry with possible values of the optimal common mode voltage duty ratio amplitude (d m ) from which the control circuitry may determine the optimal common mode voltage duty ratio amplitude (d m ).

19

19. A method of controlling a motor, comprising: determining a first possible optimal common mode voltage duty ratio which reduces the temperature differences among a plurality of solid state switching devices and associated diodes on a leg carrying maximum current in a power inverter; determining a second possible optimal common mode voltage duty ratio which causes the temperature of a plurality of solid state switching devices on a leg not carrying maximum current to equate to the temperature of the plurality of solid state switching devices on the leg carrying maximum current in the power inverter; determining a third possible optimal common mode voltage duty ratio which causes the temperature of a plurality of diodes on a leg not carrying maximum current to equate to the temperature of the plurality of solid state switching devices on the leg carrying maximum current in the power inverter; choosing an optimal common mode voltage duty ratio from among the first possible optimal common mode voltage duty ratio, second possible common mode voltage duty ratio, and third possible common mode voltage duty ratio; varying a common mode voltage duty ratio for a plurality of solid state switching devices in the power inverter according to the optimal common mode voltage duty ratio; generating drive signals for the solid state switching devices based at least in part upon the common mode voltage duty ratio; and changing states of the solid state switching devices based upon the drive signals.

20

20. The method of claim 19 , wherein choosing the optimal common mode voltage duty ratio comprises storing the amplitude of the optimal common mode voltage duty ratio in memory circuitry.

21

21. The method of claim 20 , comprising determining the first possible optimal common mode voltage duty ratio, determining the second possible optimal common mode voltage duty ratio, determining the third possible optimal common mode voltage duty ratio, and choosing the optimal common mode voltage duty ratio before a motor has begun to operate.

22

22. The method of claim 19 , comprising determining a phase angle of an output current of the inverter varying the common mode voltage duty ratio and determining the first possible optimal common mode voltage duty ratio, second possible optimal common mode voltage duty ratio, and third possible optimal common mode voltage duty ratio according to the phase angle.

23

23. The method of claim 22 , wherein varying the common mode voltage duty ratio comprises determining a phase angle of an output current of the inverter and varying the common mode voltage duty ratio according to the phase angle.

24

24. The method of claim 19 , comprising varying the common mode voltage duty ratio only when a desired output power frequency is below approximately 5 Hz.

25

25. A motor controller comprising: an inverter including a plurality of solid state switching devices and associated flyback diodes, the switching devices and diodes being interconnected to form a three phase inverter; and control circuitry coupled to the inverter and configured to vary a common mode voltage duty ratio for switching the solid state switching devices, and to generate drive signals for the solid state switching devices based upon the common mode duty ratio, and wherein the control circuitry is configured to vary the common mode voltage duty ratio such that the temperature differences between solid state switching devices and associated flyback diodes of at least one phase of power are reduced.

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Patent Metadata

Filing Date

August 28, 2007

Publication Date

November 2, 2010

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Cite as: Patentable. “Junction temperature reduction for three phase inverters modules” (US-7825621). https://patentable.app/patents/US-7825621

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