A semiconductor memory device includes plural banks, defect relief circuits individually provided for these banks, a defective-address storing circuit that stores defective addresses, and a comparing circuit that compares an access-requested address with a defective address. The defective-address storing circuit and the comparing circuit are allocated in common to two banks, respectively. With this arrangement, a chip area can be decreased.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device comprising: a plurality of banks, each of said plurality of banks including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells disposed at intersections of the plurality of word lines and the plurality of bit lines; a plurality of defect relief circuits that relieve defective bits included in the plurality of memory cells, each assigned to an associated one of a plurality of main amplifiers that access the memory cells; a plurality of defective-address storing circuits that store defective addresses, each assigned to an associated one or more of the plurality of defect relief circuits; a plurality of comparing circuits, each assigned to an associated one or more of the plurality of defect relief circuits; and a switch that connects either the plurality of defect relief circuits or the plurality of main amplifiers to a data input/output terminal based on an output signal of the plurality of comparing circuits, wherein each one of the plurality of comparing circuits includes: an X address comparing block that compares a first X address to be accessed with a second X address stored in the defective-address storing circuits, said X address comparing block being assigned to an associated one of the plurality of banks; a Y address comparing block that compares a first Y address and a first bank address to be accessed with a second Y address and a second bank address stored in the defective-address storing circuits, the Y address comparing block being assigned to an associated more than one of the plurality of banks; a selection block that selects output signals of the X address comparing block based on the bank address stored in the defective-address storing circuits; and a logic block that compares an output signal of the selection block with an output signal of the Y address comparing block.
2. The semiconductor memory device as claimed in claim 1 , wherein the switch includes: a first switch controlled by the output signal of the plurality of comparing circuits, the first switch being connected between the data input/output terminal and a read amplifier that reads data from the plurality of memory cells; a second switch controlled by the output signal of the plurality of comparing circuits, the second switch being connected between the data input/output terminal and the plurality of defect relief circuits; and a third switch controlled by the output signal of the plurality of comparing circuits and a write signal, the third switch being connected between the data input/output terminal and the plurality of defect relief circuits.
3. The semiconductor memory device as claimed in claim 1 , wherein the X address comparing block includes: a comparing block that compares the first X address to be accessed with the second X address stored in the defective-address storing circuits; and a first logic block that controls an output signal of the comparing block based on a bank active signal.
4. The semiconductor memory device as claimed in claim 3 , wherein the Y address comparing block includes: a first comparing block that compares the first Y address to be accessed with the second Y address stored in the defective-address storing circuits; a second comparing block that compares the first bank address to be accessed and the second bank address stored in the defective-address storing circuits; and a second logic block that logically synthesizes output signals of the first and second comparing blocks.
5. The semiconductor memory device as claimed in claim 1 , wherein the plurality of defect relief circuits have flip-flop circuit configuration, and the plurality of memory cells have a DRAM cell configuration.
6. The semiconductor memory device as claimed in claim 5 , wherein each of the plurality of defective-address storing circuits is an antifuse circuit that can be irreversibly changed from a nonconductive state to a conductive state, by an electrical writing operation.
7. The semiconductor memory device as claimed in claim 1 , wherein each of the plurality of comparing circuits interrupts a first coincidence signal from the X address comparing circuit based on the bank address stored in the defective-address storing circuit, and wherein each of the plurality of comparing circuits further includes a synthesizing circuit that logically synthesizes a second coincidence signal from the X address comparing circuit that is not interrupted and a third coincidence signal from the Y address comparing circuit.
8. The semiconductor memory device as claimed in claim 1 , wherein each of the plurality of main amplifiers is connected between more than one bank and the data input/output terminal, the plurality of defect relief circuits is assigned to an associated one of the plurality of main amplifiers, and each of the plurality of main amplifiers and each of the plurality of defect relief circuits are assigned to more than one banks that are assigned to a same defective-address storing circuit and a same comparing circuit.
9. The semiconductor memory device as claimed in claim 8 , wherein the plurality of defective-address storing circuits and the plurality of comparing circuits are disposed adjacent to a corresponding main amplifier.
10. The semiconductor memory device as claimed in claim 1 , wherein two or more of the plurality of banks can be brought into an active state.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 12, 2007
November 16, 2010
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